隨機計算(Stochastic Computing , SC)由於其容錯率的特質，在近年來逐漸獲得關注。與傳統的二進制計算系統不同的是，隨機計算是以一串位元流來表示一個機率值。而其電路的設計可以使用低成本的邏輯閘組合來完成複雜的計算，藉以降低硬體的大小，節省成本。
然而，以往隨機計算的應用領域被限制在類神經網路、控制系統、影像處理還有低密度同位元檢查碼上。而本論文的目標是去探索更多可能的應用，故本論文嘗試實作了三種基於隨機計算的應用。 第一種應用是繪製貝茲曲線電路的設計，由於貝茲曲線的計算公式可以使用Berstein polynomial來表示，而Berstein polynomial在隨機計算上可以使用簡單的邏輯閘組合來實現，所以貝茲曲線的繪製可以有效的利用隨機計算的特性來完成電路的設計。但是，我們的模擬結果顯示繪製的效果並不理想，儘管增加了位元流的長度，仍然無法接近理想上的曲線。而本論文也嘗試實作了基於線性內積模組的隨機離散餘弦轉換電路，然而使用在圖像處理上會有明顯的區塊化影響，造成圖像的失真。
最後，本論文提出基於隨機計算之去尾迴旋碼解碼器。其與傳統的二進制維特比(Viterbi)解碼器不同，不同的地方在於本論文是將去尾迴旋碼視為一種區塊碼，而其解碼器的設計是基於低密度同位元檢查碼的原理。由於變數節點(Variable Node)單元會因為同位元檢查矩陣的關係，導致硬體的電路過大。故本論文提出一個電路架構，藉由合併與篩選從檢查節點(Check Node)單元傳送給變數節點單元的資訊，藉以降低變數節點單元的輸入數，進而節省硬體的面積。而本論文是針對LTE之去尾迴旋碼標準而設計隨機解碼器，該標準之編碼長度為40-bits的標準所設計的解碼器。與傳統的維特比解碼器相比，本論文所提出的解碼器能節省超過60%的硬體面積。此外，本論文所提出的解碼器，解碼效能也比傳統的維特比解碼器要好。而我們的模擬結果也顯示，比較小的編碼長度，解碼效能還能比較長的編碼長度來的好。

Stochastic computing (SC) has recently gained attention due to its fault-tolerance property. Different from the ordinary binary computing, this unconventional approach represents numbers using the probability value of bit-streams. Very low-cost circuits that are highly resistant to manufacturing process variations and soft errors can thus be designed by stochastic logic. However, SC applications have been limited to the fields of neural networks, control systems, image processing, and low-density parity code (LDPC) applications. This thesis aims to explore more possible SC applications. In this thesis, three applications have been explored. The first application is the rendering of Bezier curve which can be expressed as a Berstein polynomial and efficiently realized by SC. However, our simulation results show the quality of rendering result is not good, and can hardly approximate the ideal curve even with the increase of length of bit-stream used. Our thesis also considers the implementation of discrete cosine transform (DCT) based on the inner-product SC circuit. However, it will lead to obvious blocking effect if DCT is applied to image coding. Finally, this thesis proposed a novel implementation of SC decoder for tail-biting convolution code. Different from the ordinary Viterbi-based decoding approach, this thesis treated the tail-biting convolution code as a block code which can be further decoded based on the decoder architecture used for LDPC. The parity relationship of a convolution code may involve dozens of bits which may lead to very high implementation cost for variable node unit. This thesis proposed a simplified scheme by merging the check-to-variable messages in order to limit the number of variable-node input messages. Our implementation results show that for the tail-biting convolution code specified in LET (Long Term Evolution) standard with the block size of 40, more than 60% area can be saved for the proposed decoder compared with the ordinary Viterbi decoder implementation. In addition, the bit-error-ration (BER) of the proposed decoders is also better. Our simulation results also show that the BER achieved based on our decoder architecture will become better for smaller block sizes.

論文審定書 i
摘要 ii
Abstract iv
目錄 vi
圖次 ix
表次 xii
第一章 概論 1
1.1 論文背景與動機 1
1.2 論文大綱 2
第二章 隨機計算背景與相關研究 3
2.1 隨機計算的數值表示方式 3
2.2 隨機計算的基本運算元件介紹 3
2.2.1 隨機乘法器 4
2.2.2 隨機加法器與隨機減法器 5
2.2.3 方程式合成 6
2.2.4 內積單元之隨機電路設計 7
2.2.5 互斥或閘與J-K正反器在隨機電路的應用 8
2.3 隨機亂數產生器設計原理 10
2.4 隨機計算的容錯率 12
2.5 隨機計算近年來相關應用 13
第三章 以隨機計算實現錯誤更正碼 16
3.1低密度同位元檢查碼 16
3.1.1 Tanner Graph 16
3.1.2 和積演算法 18
3.2 使用隨機計算實現和積演算法 22
3.2.1初始化 22
3.2.2 檢查節點運算 22
3.2.3 變數節點運算 23
3.2.4 字碼的硬判定(Hard Decision) 25
3.3 變數節點在隨機計算下的栓鎖問題與解決方法 26
3.3.1 雜訊相依性調整(Noise-Dependent Scaling , NDS) 27
3.3.2邊緣記憶體(Edge Memory , EM) 28
3.3.3 循跡預測記憶體(Tracking Forecast Memory , TFM) 32
3.3.4 基於多數決機制的循跡預測記憶體(Majority- Based Tracking Forecast Memories ，MTFM ) 33
3.3.5 基於多數決機制的邊緣記憶體(Majority Edge Memory , MEM) 37
3.4 去尾迴旋碼介紹 39
3.4.1 去尾迴旋碼編碼方法 40
3.4.2產生去尾迴旋碼之生成矩陣 41
3.4.3產生去尾迴旋碼之同位元檢查矩陣 42
第四章 基於隨機計算之影像處理應用實作 44
4.1貝茲曲線 44
4.2離散餘弦轉換(DCT) 45
第五章 基於隨機計算之去尾迴旋碼解碼器實作 50
5.1 生成矩陣與同位元檢查矩陣產生 50
5.2 硬體架構 51
5.2.1 通道機率隨機亂數產生器(Channel Probability Stochastic Number Generator , CPSNG) 54
5.2.2 亂數產生引擎(Random Number Engine, RNE) 54
5.2.3 檢查節點(Check Node , CN) 55
5.2.4 變數節點(Variable Node, VN) 56
5.2.5 字碼硬判定(Hard Decision , HD) 60
5.2.6 提早結束機制(Early Termination , ET) 61
5.2.7 控制器(Controller) 62
5.3 軟體驗證與FPGA驗證 62
5.3.1 軟體驗證 62
5.3.2 FPGA 驗證 63
第六章 實驗結果與效能比較 66
6.1 貝茲曲線實驗結果 66
6.2離散餘弦轉換(DCT)實驗結果 67
6.3 基於隨機計算之去尾迴旋碼解碼器實驗結果與效能比較 68
6.3.1解碼效能分析與硬體面積比較 68
6.3.2 去尾迴旋碼不同截斷長度之效能比較 71
第七章 結論與未來展望 73
7.1 結論 73
7.2 未來展望 73
參考文獻 74
附錄A 固定取18條輸入的變數節點與檢查節點對應表格 77
附錄B 40-bits去尾迴旋碼解碼器之同位元檢查矩陣 81

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