隨著對移動裝置中圖學應用的要求增加，如何設計有效率的嵌入式繪圖處理單元已是個熱門的議題。在先前已提出一個多功能貼圖單元，此單元能提供與像素上色相關的功能，其中包含不同模式的著色效果與貼圖。本論文首先將整合多功能貼圖單元於一個能加速描繪與點陣化的向量圖形處理器。藉著整合這兩個模組能完成一個有效率的向量圖形渲染處理器，並達成在顯示裝置上渲染向量圖形物件的目的。而為了在著色程式執行時提供多樣性的貼圖功能，本論文也將多功能貼圖單元整合於一個三維的多執行緒統一著色處理器。將多功能貼圖單元分別整合於向量與三維繪圖處理器後，需進行包裝使其可以掛載於advanced- microcontroller-bus-architecture (AMBA)系統上。此外，在整合前多功能貼圖單元與向量圖形處理器僅通過RTL模擬驗證，而本論文已將兩個整合完的處理器於FPGA上模擬驗證成功，並且能在System-on-a-Programmable-Chip (SOPC)平台上執行展示程式。

With the increasing demand of graphics applications in mobile devices, how to design an efficient embedded graphics processor unit (GPU) has become a hot issue. A multi-function texture unit has been proposed in the past, which can provide the related pixel-coloring functions including different modes of painting and texturing.
This thesis first integrates this versatile texture unit with a vector graphics accelerator which can accelerate the processes of tessellation and rasterization. By integrating these two modules together, an efficient vector-graphics rendering processor can be achieved, which can render the vector graphics objects into the display devices. Next, the multi-function texture unit has also been integrated with a three-dimensional (3D) unified multi-thread shader processor in order to provide various kinds of texture functions during the execution of shading programs. Both vector and 3D graphics processors after being integrated with the multi-function texture unit have been wrapped with advanced-microcontroller-bus-architecture (AMBA) interfaces such that both can be hooked on AMBA-based systems. The multi-function texture unit and the vector graphics accelerator can only pass RTL simulation before integration. But now both integrated processors have been successfully synthesized using FPGA, and can run demo programs on the System-on-a-Programmable-Chip (SOPC) platform.

論文審定書………………………………………………………………………………i
摘要 .............................................................................................................................. ii
Abstract ....................................................................................................................... iii
圖次 ............................................................................................................................. vi
方程式索引 ................................................................................................................. ix
Chapter 1概論 .............................................................................................................. 1
1.1研究動機 ........................................................................................................ 1
1.2論文大綱 ........................................................................................................ 2
Chapter 2 研究背景與相關研究 .................................................................................. 3
2.1 電腦圖學介紹 ................................................................................................ 3
2.1.1 二維繪圖介紹 ..................................................................................... 3
2.1.2三維繪圖介紹 ...................................................................................... 6
2.2 多功能貼圖單元[1] ....................................................................................... 6
2.2.1 多功能貼圖單元[1]功能介紹.............................................................. 7
2.2.2 多功能貼圖單元[1]硬體介紹............................................................ 12
2.3 向量圖形處理器[2] ..................................................................................... 17
2.3.1向量圖形處理器[2]功能介紹 ............................................................ 18
2.3.2向量圖形處理器[2]硬體介紹 ............................................................ 21
2.4 三維繪圖處理器[3] ..................................................................................... 24
Chapter 3 多功能貼圖單元與繪圖處理器之整合 ..................................................... 26
3.1多功能貼圖單元與向量圖形處理器之整合 ................................................. 26
3.2多功能貼圖單元與三維繪圖處理器之整合 ................................................. 33
Chapter 4 驗證與結果分析 ....................................................................................... 37
4.1 EASY平台驗證 ........................................................................................... 37
v
4.2 FPGA板驗證................................................................................................ 41
4.2.1 驗證過程 ........................................................................................... 42
4.2.2 驗證結果 ........................................................................................... 44
Chapter 5 結論與未來目標 ....................................................................................... 45
5.1結論 .............................................................................................................. 45
5.2未來目標 ...................................................................................................... 45
參考文獻 .................................................................................................................... 46

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