隨著半導體產業不斷的進步，以及人們對於3C電子產品越輕越薄的需求下，電子封裝技術的要求也逐漸與日俱增。覆晶封裝製程是近年來較為新穎的封裝技術，特別是內嵌式銅軌基板的熱覆晶封裝製程，不同於以往基板的設計，將銅軌線路內嵌於基板中，藉此以達到降低封裝晶片厚度及提升晶片效能的目的。但由於目前封裝產業對此熱覆晶封裝製程中的相關參數和內嵌式銅軌基板的變形機制尚未完全了解，故本研究將針對此內嵌式銅軌基板的翹曲做相關的探討。
本研究利用有限元素模擬軟體ANSYS進行內嵌式基板的模型建立與熱變形相關的探討分析，但因內嵌式銅軌基板的內部結構具有高度非對稱性與複雜的銅軌分布，在有限元素模擬軟體的模型建立上不僅十分困難，所需的求解資源也十分龐大，本研究以面積占有比例來等效與簡化複雜的基板結構，分析簡化模型的翹曲變形情形，找出基板變形的機制。使用有限元素模擬及結合田口方法，分析各個尺寸變數對於基板翹曲的影響，進而最佳化基板尺寸的製程參數。有限元素模擬的解析結果也與實驗結果比對以驗證模擬結果分析的可行性，最後提供最佳化製程參數供給基板設計端作為參考準則。

With the advance of the semiconductor industry and in response to the demands of ultra-thin electronic products, packaging technology has been continuously developed. Thermal bonding process of copper pillar flip chip package is a new bonding process in packaging technology, especially for the substrate with embedded copper traces, different from the substrate design before, replaced the protruding copper traces into the embedded copper traces to reduce the thickness of the substrate. However, due to the current packaging industry, the deformation mechanism and the relevant parameters of the packaging process of embedded copper trace substrate are not clear, this study will discuss the thermal deformation of the embedded copper trace substrate.
Finite element simulation software “ANSYS” used in this study to analysis the thermal deformation of embedded copper trace substrate and establish the substrate model, however, the internal structure of the embedded copper trace substrate has a high degree of asymmetry and complex copper trace distribution, it’s not only difficult to establish model in finite element simulation software but also required huge resources to solve. Area occupation ratio was applied in this study to simplify the complex copper trace structure, analyze the simplify structure and try to find out the deformation mechanism of the substrate. Taguchi method also applied into established finite element simulation model, discussing the effect of the various structure variables of the substrates, thereby optimizing the package process parameters of the substrate. Finite element analysis results also compare to the experiment measurement results to verify the reliability of simulation results, finally supplied the optimization process parameters to the substrate designer as a reference criterion.

論文審定書 i
謝誌 ii
摘要 iii
Abstract iv
目錄 v
圖目錄 viii
表目錄 xi
符號說明 xii
第一章 緒論 1
1.1 前言 1
1.2 電子封裝技術簡介 3
1.2.1 電子封裝發展歷程 3
1.2.2 電子封裝層級 5
1.2.3 積體電路晶片與電路基板連接方式 6
1.3 覆晶封裝製程與內嵌式銅軌基板之簡介 7
1.3.1 銅柱覆晶發展簡介 7
1.3.2 銅柱覆晶封裝回焊製程簡介 8
1.3.3 銅柱覆晶封裝之應用 9
1.4 文獻回顧 10
1.5 研究動機與目的 14
1.6 論文架構及研究流程 15
第二章 內嵌式銅軌基板翹曲行為之有限元素分析 17
2.1 前言 17
2.2 內嵌式銅軌基板之三維熱變形分析 18
2.2.1 有限元素軟體ANSYS簡介 18
2.2.2 三維有限元素模擬基本假設與幾何尺寸簡介 19
2.2.3 內嵌式銅軌基板之三維等效幾何模型 22
2.2.4 內嵌式銅軌基板之材料特性 26
2.2.5 有限元素分析邊界條件設定與網格劃分 27
2.2.6 三維熱變形解析結果 31
2.3 基板三維熱變形有限元素分析之探討 46
2.3.1 有限元素網格收斂性分析 46
2.3.2 基板三維熱變形有限元素分析結果線性回歸 48
第三章 製程參數之最佳化分析 55
3.1 田口實驗法簡介 55
3.1.1 田口實驗法背景 55
3.1.2 多水準因子實驗方法簡介 55
3.1.3 品質損失函數 59
3.2 田口實驗法結合三維有限元素分析 62
3.2.1 前言 62
3.2.2 與銅材料相關變數之田口法分析 63
3.2.3 與阻焊劑材料相關變數之田口法分析 68
第四章 內嵌式銅軌基板翹曲解析結果與實驗結果之比較 72
4.1 光學量測技術簡介 72
4.2 量測結果與解析結果之比較 78
第五章 結論 84
5.1 內嵌式銅軌基板翹曲行為之三維有限元素解析結果 84
5.2 田口方法結合三維有限元素分析結果 85
5.3 實驗與解析結果比較 86
5.4 今後課題與未來方向 86
參考文獻 87

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