隨著嵌入式系統的快速發展，系統功能越來越多且晶片速度越來越快，多核心架構已經成為一項趨勢，然而由於複雜的多核心架構使得軟硬體的效能分析與驗證變得更加困難，導致系統效能分析與整合驗證的時間過長。電子系統層級(ESL
)工具不僅可以大幅減少軟硬體設計的時間，也可提早對於產品的效能以及穩定度加以改善。QEMU-SystemC是一個軟硬體驗證模擬平台，其完整的系統行為模擬使得可以在上面執行較複雜的軟體，如作業系統。因應多處理器架構的普及化，QEMU可模擬許多多處理器架構，然而由於設計上的限制，例如:動態轉譯與TB(Translation Block) Chaining機制造成效能分析上的困難。因此，本論文題出在QEMU-SystemC平台中之多處理器效能分析方法，藉由在TB中嵌入效能分析指令，使得可以在不破壞模擬架構的情形下，動態追蹤正在執行的TB資訊，並透過多處理器之時間模型與多處理器之間的時間同步機制來評估多處理器平台下之系統執行時間。另外，在加入效能分析的方法後，勢必會增加模擬時間成本，因此我們提出三種不同時間精確度的模擬層級，依據時間評估的準確度不同所造成的模擬時間成本也不同，藉此讓使用者在模擬時間與評估準確度之間做取捨。

With the development of embedded systems, there are more and more functions in the system and the chip speed increasingly faster and faster. Multiprocessor architecture has become the trend of chip design. The complexity of the multiprocessor architecture makes the hardware and software performance analysis and verification more difficult, it resulting in the time for system performance analysis and integration verication time is too long. Electronic system level (ESL) tools can not only significantly reduce the time for designing hardware and software, but also can improve the performance and stability in early. QEMU-SystemC is a simulation platform for hardware/software verification that can simulate a complete system behavior so that some complex software such as OS can run on the platform. With the popularity of multi-processor architecture, QEMU can emulate many multi-processor architectures, however, due to the constraints of design, such as: Dynamic Translation and Translation Block Chaining mechanism that make performance analysis difficult. Therefore, this thesis presents a multiprocessor performance analysis method in QEMU-SystemC platform that can trace the TB information in runtime by insert some instructions to the TB without destroyting the simulator architecture. And it can evaluate the system execution time by using multiprocessor timing models and the multiprocessor timing synchronization mechanism. Besides, the performance analysis model must increase the cost of simulation time. Therefore, we proposed three simulation mode that simulate at different timing accuracy. The cost of simulation time depends on the different timing accuracy.

論文審定書 i
中文摘要 iii
Abstract iv
Contents v
List of Figures vii
List of Tables viii
Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Background 1
Chapter 2. Related Works 4
2.1 Preliminary ESL Simulation Tools 4
2.1.1 QEMU 4
2.1.2 SystemC 6
2.1.3 QEMU-SystemC Co-Simulation Platform 6
2.2 Simulation-Based Performance Analysis 7
2.2.1 Cycle-Accurate Simuation 7
2.2.2 Functional-Accurate Simulation 7
2.3 Performance Measurement Tools 7
2.4 QEMU Timing Models 8
Chapter 3. Multi-Processor Timing Analysis in QEMU-SystemC 9
3.1 Real-Time Executed TB Tracing 10
3.2 Multi-Processor Timing Model 12
3.3 Multi-Processor Timing Synchronization in QEMU 13
3.4 Versatile Timing Evaluation 15
3.4.1 Evaluation Modes 16
3.4.1.1 Accurate Mode 17
3.4.1.2 Approximate Mode 17
3.4.2 Selective Software Module Analysis 18
Chapter 4. Visualization of Timed QEMU-SystemC Multiprocessor Simulation 21
Chapter 5. Experiment Result 24
5.1 Overhead of Real-time TB Tracing 24
5.2 Evaluation Accuracy and Overhead 27
Chapter 6. Conclusion 36
Chapter 7. Future Work 37
References 38

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