曲面細分著色器是最先進的圖學標準應用編程介面(如OpenGL 4.x和DirextX 11)支援的高階圖學渲染功能之一。它提供了將patch的頂點資訊細分成較小的基元的編程能力。而細分過程在圖學管線中可以分為三個階段：Tessellation Control Shader (TCS)，Tessellation Primitive Generation (TPG)和Tessellation Evaluation Shader (TES)。本論文提出了一個有效率的曲面細分單元設計來實現TPG的固定功能和一個可以將由曲面細分所產生的頂點組合成一堆三角形的基元組合單元。TPG分為兩個階段來實現，其中一個為建立階段，用於計算新的同心內三角形的頂點和邊緣的細分向量；另一個為生成階段，使用從前一個階段獲得的細分向量來生成三角形邊緣上的頂點。為了避免硬體成本高的除法器單元，將儲存在查找表中預先計算的倒數分子做相乘以取代所需的除法運算。我們提出的TPG實現的一個特點是利用從最外面的三角形patch創建的所有同心內三角形的三個頂點的總和與減少三分之一所產生的內三角形所需的加減運算次數是一樣的。整個TPG單元只需要兩組加法器和一組乘法器。其硬體合成數據結果為使用了約25K個邏輯閘，並且在90nm技術下能運行到166.7MHz。本論文提出的基元組合單元會將兩個連續的同心內三角形的區域分成六組扇形三角形來組合三角形。

Tessellation shader is one of the advanced graphics rendering functions supported in state-of-the-art graphics standard applications programming interfaces such as OpenGL 4.x and DirextX 11. It provides the programming capability to divide the patches of vertex data into smaller primitives. The tessellation procedure in the graphics pipeline can be divided into three stages: tessellation control shader(TCS), tessellation primitive generation(TPG) and tessellation evaluation shader(TES). This thesis proposes an efficient design of tessellation unit to realize the fixed functions of TPG and the primitive assembly unit(PAU) that can assemble the vertices generated by tessellation into a bunch of triangles. TPG is realized by two-stage pipeline, which includes a setup stage to calculate the vertices of new concentric inner triangles and the edge’s subdivision vector followed by the other stage to serially generate the vertices on the triangle’s edges based on the vectors obtained from the preceding stage. To avoid the expensive divider unit, the required division operation is substituted by multiplying the pre-computed reciprocal factor stored in on-chip look-up tables. One of the salient features of our proposed TPG implementation is to reduce the number of addition/subtraction operations required for generating inner triangles by two thirds by exploring the feature that the sum of three vertices of all concentric inner triangles will be the same. The entire TPG unit only requires two pairs of adders and one pair of multipliers. Its overall gate count is about 25K, and it can run up to 166.7 MHz under 90nm technology. The PAU proposed in this thesis will assemble triangles by dividing the regions of two successive concentric inner triangles into six groups of triangle fans.

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
方程式索引 ix
CHAPTER 1 概論 1
1.1 研究動機 1
1.2 論文大綱 2
CHAPTER 2 研究背景與相關研究 3
2.1 三維繪圖管線流程 3
2.2 三維繪圖處理器背景 6
2.3 曲面細分(TESSELLATION) 10
2.3.1 曲面細分介紹 10
2.3.1.1 Tessellation Control Shader 11
2.3.1.2 Tessellation Evaluation Shader 12
2.3.1.3 Tessellation Primitive Generator 13
2.3.2 曲面細分相關研究 14
CHAPTER 3 曲面細分架構設計 18
3.1 曲面細分流程 18
3.2 曲面細分單元硬體架構 19
3.2.1 控制單元介紹 20
3.2.1.1 三角形(Triangle) 20
3.2.1.2 四邊形(Quad) 25
3.2.1.3 等值線(Isolines) 29
3.3 唯讀記憶體(ROM) 30
3.4 曲面細分單元排程器 31
3.5 基元組合單元(PRIMITIVE ASSEMBLY UNIT) 33
3.5.1 三角形(Triangle) 33
3.5.2 四邊形(Quad) 37
CHAPTER 4 曲面細分單元與三維繪圖處理器之整合 41
4.1曲面細分單元與三維繪圖處理器整合架構 41
4.2三維繪圖處理器修改與設計 43
4.2.1 處理器上層流程控制 43
4.2.2 排程器資料流程 45
CHAPTER 5 結果分析 52
5.1 硬體使用率 52
5.2 硬體成本 54
5.3 效能速度 55
CHAPTER 6 結論與未來目標 57
6.1 結論 57
6.2 未來目標 57
參考文獻 59

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