本論文提出以主動放大器回授(Active amplifier feedback)和虛開關(Dummy switch)完成之切換電流積分器來降低傳統切換電流電路中存在的非理想效應 , 進而完成切換電流式積分三角調變器.我們以主動放大器回授改善電路中存在的 transmission error 且提高工作速度 ,並採用虛開關來降低脈衝穿透效應(Clock feedthrough)所造成的誤差,以達到高解析度之目的.


在系統電路實現,我們以TSMC 0.35μm CMOS 製程進行模擬,在訊號頻寬為40KHz、 取樣頻率10.24MHz、超取樣率為128、供應電壓3.3V之條件下, 得到67dB之最大訊號雜訊比和66dB之動態範圍,消耗功率為19mW.

In this thesis, a switched-current integrator with active amplifier feedback and dummy switch is proposed to increase the operation speed and reduce the non-ideal effects in traditional switched-current circuit. The active amplifier is designed in low gain and high bandwidth so that the oscillation can be avoided. We improve the operation speed and transmission error by the active amplifier feedback and reduce the CFT error by the dummy switch so that high resolution can be achieved. Then we apply the proposed integrator to the switched-current sigma-delta modulator.


The sigma-delta modulator is simulated using TSMC 0.35μm CMOS process with 3.3V power supply. We obtain 67dB PSNR, 66dB dynamic range(DR), and 40KHz bandwidth. The sampling frequency is 10.24MHz, the power supply is 3.3V and the power consumption is 19mW.

CHAPTER 1
INTRODUCTION…………………………………...……………………………….1
1.1 BACKGROUND.......................................................................................................1
1.2 THESIS ORGANIZATION.......................................................................................5

CHAPTER 2
SWITCHED-CURRENT TECHNIQUE....................................................................6
2.1 SWITCHED-CURRENT CIRCUIT..........................................................................6
2.2 SWITCHED-CAPACITOR CIRCUIT......................................................................8
2.3 COMPARISON BETWEEN SWITCHED-CURRNET AND SWITCHED-
CAPACITOR CIRCUIT............................................................................................9
2.4 NON-IDEAL BEHAVIORS OF SWITCHED-CURRENT CIRCUIT...................10
2.4.1 MISMATCH ERRORS.................................................................................10
2.4.2 FINITE INPUT/OUTPUT IMPEDANCE....................................................12
2.4.3 CLOCK FEEDTHROUGH EFFECT AND CHARGE INJECTION..........16
2.4.4 SETTLING TIME ERROR..........................................................................20

CHAPTER 3
SIGMA-DELTA MODULATOR...................................................................................22
3.1 NYQUIST SAMPLING RATE AND QUANTIZATION ERROR........................22 3.1.1 NYQUIST SAMPLING RATE....................................................................22
3.1.2 QUANTIZATION ERROR..........................................................................23
3.2 TECHNIQUES OF SIGMA-DELTA MODULATOR............................................25
3.2.1 OVERSAMPLING.......................................................................................25
3.2.2 NOISE SHAPING.........................................................................................27
3.3 SYSTEM ARCHITECTURE OF SIGMA-DELTA A/D CONVERTERS.............28
3.3.1 FIRST-ORDER SIGMA-DELTA MODULATOR......................................29
3.3.2 SECOND-ORDER SIGMA-DELTA MODULATOR.................................32

CHAPTER 4
THE PROPOSED SIGMA-DELTA MODULATOR WITH ACTIVE AMPLIFIER INTEGRATOR……………………………………………………...35
4.1 DESIGN FLOW.....................................................................................................35
4.2 THE PROPOSED CIRCUIT..................................................................................36
4.2.1 INTEGRATOR.............................................................................................36
4.2.2 1-BIT CURRENT QUANTIZER.................................................................45
4.2.3 1-BIT D/A CONVERTER............................................................................45
4.2.4 LATCH.........................................................................................................46
4.3 THE COMPLETED SECOND-ORDER SWITCHED-CURRENT SIGMA-DELTA MODULATOR..........................................................................47

CHAPTER 5
SIMULATION RESULT OF THE PROPOSED SECOND-ORDER SWITCHED-CURRENT SIGMA-DELTA MODULATOR……………………49

5.1 THE PROPOSED MEMORY CELL.....................................................................49
5.2 QUANTIZER.........................................................................................................53
5.3 DIGITAL TO ANALOG CONVERTER (DAC)..................................................55
5.4 THE PROPOSED SECOND-ORDER SIGMA-DELTA MODULATOR............55

CHAPTER 6
CONCLUTIONS……………………………………………………………………60

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