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博碩士論文 etd-0812110-140803 詳細資訊
Title page for etd-0812110-140803
論文名稱
Title
一個低雜訊、寬頻範圍延遲鎖定迴路利用軌對軌差動型多種(類比與數位)控制延遲線來實現
A low Jitter Wide-range Delay-Locked Loop with the Rail to Rail Differential Multi Control Delay Line Implementation
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
83
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-07-28
繳交日期
Date of Submission
2010-08-12
關鍵字
Keywords
互補式金氧半、延遲鎖定迴路、多重相位、鎖相迴路
CMOS, Delay-locked loop, Multiphase, Phase-locked loop
統計
Statistics
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中文摘要
本論文提出一個以軌對軌差動型控制延遲線延及利用多個不同頻段的KVCDL來產生寬頻範圍頻率遲鎖定迴路(DLL)。因為易於設計以及穩定性佳的優點,延遲鎖定迴路(delay locked loop, DLL)已經比鎖相迴路(phase locked loop, PLL)更廣泛地應用在時脈誤差調整上。
在本論文中主要針對延遲鎖定迴路(DLL)和軌對軌差動型控制延遲線作出說明以及討論,並且使用TSMC 0.18μm 1P6M CMOS Process,供應電壓為1.8V;設計出一個70MHz∼750MHz延遲迴路。
本論文主要特色是利用軌對軌的的輸入級,能減少雜訊的干擾,又可以增加信號的完整性(低失真、低雜訊、低功率消耗和較高的頻寬增益),並且利用相位選擇器(phase selection circuit)來延展頻寬範圍。其延遲鎖定迴路(DLL)的輸入範圍為70MHz∼750MHz,整個系統的功率消耗小於 32mW。相位誤差在70MHz與 750MHz時分別為10ps與 <10ps,本論文所提出的延遲鎖定迴路可提供寬頻範圍的鎖定與低抖動的特色。
Abstract
A Rail to Rail Differential Control Delay Line using multi-band technology can provide wider range on a delay-locked loop (DLL) is proposed in this thesis. Delay-Locked Loops (DLLs) have been widely used for clock deskew instead of Phase-Locked Loop (PLLs) because of easy design and inherent stable.
The main object of this thesis is the description and discussion in Delay-Locked Loop and Rail to Rail Differential Control Delay Line; uses TSMC 0.18μm 1P6M CMOS process to design a 70 MHz∼750 MHz DLL and the supply voltage is 1.8V.
This thesis is characterized by utilizing rail to rail input to reduce noise interference and enhance the signal integrity(low distortion, low noise, low power and high gain).By the phase selection circuit is used to extend operation frequency. The operate frequency range of DLL is 70MHz to 750MHz, the power consumption of the Entire system is less than 32mW. The phase error is 10 ps at 70MHz and <10 ps at 750MHz in lock. The proposed DLL can provide wider range and lower jitter in this thesis.
目次 Table of Contents
Chapter 1 11
Introduction .................................................................................................. 11
1.1 Motivation .............................................................................................. 11
1.2 Research Goals....................................................................................... 12
1.3 Thesis Organization ............................................................................... 13
Chapter 2 14
Introduction of the Basic Concepts of Delay-locked Loop ......................... 14
2.1 DLL Overview ....................................................................................... 14
2.2 Jitter........................................................................................................ 15
2.2.1 Clock Jitter .......................................................................................... 16
2.2.2 Types of Jitter ...................................................................................... 16
2.2.3 Cycle-to-Cycle Jitter [13] ................................................................... 17
2.2.4 Period Jitter [13] ................................................................................. 18
2.2.5 Long-term Jitter .................................................................................. 21
2.3 Clock Skew ............................................................................................ 22
2.4 Lock Range ............................................................................................ 23
2.4.1 Harmonic Locking .............................................................................. 26
2.4.2 Stuck Locking ..................................................................................... 27
2.4.3 Phase Noise ......................................................................................... 28
2.5 Phase Detector (PD) / Phase Frequency Detector (PFD) ....................... 30
2.6 Charge Pump (CP) and Loop Filter (LF) ............................................... 33
2.7 Voltage-controlled Delay Line (VCDL) ................................................ 34
2.7.1 The Current-starved Delay Cell .......................................................... 35
2.7.2 Differential Delay Elements with Symmetric Loads .......................... 36
2.8 Stability Analysis of the Delay-Locked Loop ........................................ 41
2.8.1 Design Consideration of the Delay-Locked Loop .............................. 43
Chapter 3 46
The Design of Low Power Precise Multi Delay-locked Loop with
Wide-Range Locking ................................................................................... 46
3.1 Introduction [25] .................................................................................... 46
3.2 The concept of rail to rail ……………………………………………..47
3.3 Architecture of Multi Rail to Rail Differential DLL .............................. 47
3.3.1 Phase Detector [24] ............................................................................. 49
3.3.2 Charge Pump and Loop Filter ............................................................. 50
3.3.3 Multi-controlled Delay Line [27] ........................................................ 52
3.3.4 Start-up Circuit.................................................................................... 61
8
3.3.5 Phase selection circuit ......................................................................... 61
3.4 Simulation Results ................................................................................. 63
3.4.1 Simulation of PD................................................................................. 63
3.4.2 Simulation of CP ................................................................................. 64
3.4.3 Simulation of Start up ......................................................................... 65
3.4.4 Simulation of Phase selection circuit .................................................. 65
3.4.5 Simulation of MCDL .......................................................................... 67
3.4.6 Simulation Result of DLL ................................................................... 70
3.5 Layout of Chip ....................................................................................... 78
Chapter 4 79
Conclusions .................................................................................................. 79
4.1 Conclusion ............................................................................................. 79
Reference 80
參考文獻 References
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