本論文採用逐次逼近暫存器(successive approximation register, SAR)來在延遲鎖定迴路(delay-locked loop, DLL)控制數位延遲線以達到非常快速的鎖定效果，並由一個迴路狀態電路(loop state controller, LSC)來休眠大部分的電路來達到低耗電的效果。因為相較於鎖相迴路(phase-locked loop, PLL)更容易於設計以及穩定性高的優點，延遲鎖定迴路(DLL)在高頻的狀態下被更廣泛的應用在時脈誤差的調整上。
在此延遲鎖定迴路的回饋路徑上加入一個暫存器與利用多工器來選擇延遲線所要的讀入的n-bit數位控制碼；當迴路達到鎖定的時候，選擇的是通過暫存器這條路徑來進入休眠狀態，並停部分電路使之進入省電模式。當進入休眠狀態後，暫存器一面提供固定的輸入，相位錯誤比較器(phase error comparator, PEC) 會不斷的追蹤是否有發生製程、電壓、溫度與負載的變化(process, voltage, temperature, and load, PVTL)而導致輸入頻率的改變。一旦發生改變，PEC便會發出訊號告知給迴路選擇控制(loop state controller, LSC)去致能關閉狀態下的電路，重新去鎖定時脈，最多只需要6個cycle即可完成重新鎖定，可鎖定的範圍約從150MHz到900MHz。在鎖定模式的功率消耗約為15mW，而在睡眠狀態下DLL的功率消耗約為9mW。

A successive approximation register (SAR) circuit is adopted to control the digital delay line in the delay-locked loop (DLL) to achieve very fast locking effect in this proposed thesis. And in order to get low power consumption results, a loop state controller (LSC) is utilized to disable most of circuit. Because it is more easily to design and the advantages of high stability of delay-locked loop (DLL) compared to phase-locked loop (PLL), delay-locked loop (DLL) is more widely used in the adjustment of the clock error in the high frequency situation.
This proposed delay locked loop (DLL) is added a register and a multiplexer in the feedback path. And the multiplexer does select which n-bit digital control code shall be read into the delay line; as the loop is locked, the path goes through the register is chosen to enter the sleep state ,and disable part of the circuit to make it into power saving mode. When entering the sleep state, the register provides the fixed input code; the phase error comparator (PEC) will keep tracking whether the frequency changes due to process, voltage, temperature and load (PVTL) variation uninterruptedly. Once there is something changed, the PEC will send a signal to inform the loop state controller (LSC) to enable the circuit from the sleep state, when the clock has to be locked again. And it just has 6 cycles time to relock, the lock range is form 150MHz to 900MHz. The power consuming are 15mW in lock mode and 9mW in sleep mode.

Chapter 1
Introduction ……………………….. ……..………………………….. .…………...…1
1.1 Motivation………………………………………………………………... 1
1.2 Research Goals…………………………………………………………… 2
1.3 Thesis Organization………………………………………………………....2
Chapter2
Introduction of Delay-Locked Loop Basic Concepts…………………………..….…3
2.1 Skew…………………………………………………………………….…..3
2.2 Jitter……………………………...…………………………………….……5
2.2.1 Categories of Jitter…………………………………….……………..5
2.2.2 Clock Jitter…………………………………………………………………………………….6
2.2.3 Cycle-to-Cycle Jitter ……………………………………………………………………….7
2.2.4 Period Jitter …………………………………………………………………………………….7
2.2.5 Long-term Jitter……………………………………………………………………………10
2.3 Lock Range………………………………………………………………..11
2.3.1 Harmonic Locking…………………………………………………………………………14
2.3.2 Stuck Locking………………………………………………………………………………..15
2.4 Frequency Synchronization……………………………………………………………………..16
2.4.1 PLL-based clock generator…………………………………………………………….16
2.4.2 DLL-based clock generator……………………………………………………………17
2.5 Main elements of digital DLL……………………………………….…….17
2.5.1 Phase Detector (PD) / Phase frequency Detector (PFD)……....……..17
2.5.1.1 Static Phase Detector………………….…………………...19
2.5.1.2 Conventional static Phase Detector………………………..19
2.5.1.3 Dynamic phase detector…………………………….……...20
2.5.2 The Digital Delay Line Controller…………………………………21
2.5.2.1 Register-controlled……………………………...…………22
2.5.2.2 Counter-controlled………………………………………23
2.5.2.3 SAR-controlled…………………………………………….24
2.6 Digital delay line……………………………………………......................26
2.6.1 Register Shift Delay Cell………………………………………….27
2.6.2 Capacitor Shunt Delay Cell….………...……………………………27
2.6.3 Binary-Weighted Delay Cell…………..……………………………28
Chapter 3
The Design of Fast Lock Digital Delay-Controlled SAR Delay-Locked Loop with Low Power in Sleep State………………………………………………………………….30
3.1 Introduction ……………………………………………………………….………………………….30
3.2 Proposed Circuit………………………………………………………………………………………31
3.3 Phase Detector……………………………………………………………..………………………….32
3.4 Delay-Controlled CSAR (Counting type Successive Approximation Register)…………………………………………………...………………37
3.5 Digital Delay Line…………………………………………………………42
3.6 Other Parts in DLL………………………………………………………...44
Chapter 4
Simulation Result…………………………………………...………………………46
4.1 Simulation of PD...………………………………………...………………46
4.1.1 UP and DN signal...………………………………………...………..46
4.1.2 Glitch simulation...………………………………………...………...48
4.1.3 One-shot pulse simulation...…………………………………………49
4.2 Simulation of CSAR...………………………………………...…………50
4.2.1 Simulation of conventional SAR part...……………………………50
4.2.2 Simulation of counter part...…………………………………………51
4.3 Simulation of Delay Line...………………………………………………52
4.4 Simulation of DLL...………………………………………………………53
4.5 Static Phase Error…………....... …………....... ………….........................54
4.6 Comparison...……………………………………………………………56
Chapter 5
Conclusion………………………………………………………………………57
Reference…………………………….……………………………….……………...58

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