採用改良的小信號等效電路，以探討沃特拉級數方法分析矽鍺異質接面電晶
體於不同溫度時候，操作於雪崩崩潰區之線性度的特性。基於雪崩延遲引發的電
感性崩潰作為物理性模型以改良描述在矽鍺異質接面電晶體之基-集極接面的特
性。採用含有gm2, Rjc 與Ljc 的模型與量測的S 參數達到良好的吻合度。隨VCB
增加，電感與電容之非線性貢獻的相消機制越為明顯，促使元件的線性度提升。
因高溫引起非線或貢獻量下降，輸出功率出現顯著的線性度隨溫度增加而改善。
然而，包括輸出功率、增益與功率附加效率的功率性能，在高溫時，是輕微地下
降。本研究建議功率放大器應用於雪崩崩潰區，其在高溫下能夠實現出高線性度
的性能。

The linearity for SiGe HBTs at different temperatures is analyzed by the Volterra
series approach with a modified small-signal equivalent circuit to characterize the
avalanche breakdown mechanism. A physical model based on the avalanche delay
induced inductive breakdown network is introduced to modify the equivalent circuit
in the B-C junction. The good agreement between the measured S-parameters in the
avalanche regime and the modified model including gm2, Rjc and Ljc is achieved. The
increment of the linearity with increasing the VCB is significant due to cancellation
mechanism between the breakdown inductive and capacitive nonlinear contributions.
Due to the high temperature induced decrement of nonlinear contribution distortion,
the output power shows significant linearity improvement with increment of
temperature. However, output power, gain, and PAE are slightly degraded at high
temperatures. This investigation can be applied for power amplifier design in the
avalanche regime by operating at high temperature for high linearity.

論文審定書…………………………………………………………………………….i
致謝……………………………………………………………………………………ii
中文摘要…………………………………………………………………...…………iii
英文摘要……………………………………………………………………………...iv
目錄…………………………………………………………………………………....v
圖次………………………………………………………………………….……….vii
表次…………………………………………………………………………………..xii
第一章 緒論…………………………………………………………………………..1
1.1 背景介紹與研究動機………………………….……………………………1
1.2 論文架構…………………………………………………………………….4
第二章 非線性特性與沃特拉級數分析…………………………………………....5
2.1 簡介……………………………………………………………………….....5
2.2 沃特拉級數之等效電路分析…………………………………………….....5
2.3 討論沃特拉級數之侷限及適用性………………………………………...11
2.4 沃特拉級數之計算流程與驗證…………………………………………...13
2.5 非線性源的貢獻及相消…………………………………………………...15
第三章異質接面電晶體之游離衝撞效應…………………………………………..19
3.1 簡介………………………………………………………………………...19
3.2 異質接面雙載子電晶體之低階注入……………………………………...20
3.3 異質接面雙載子電晶體之衝撞游離. …………………………………….21
vi
3.4 異質接面雙載子電晶體之直流崩潰電壓………………….……………..24
3.5 倍增因子(Multiplication Factor)與萃取……………………….………….26
3.6 游離長度(Dead Space)…………………………………………………….29
3.7 克爾克效應(Kirk effect)與準飽和(quasi-saturation)………….…………..31
第四章 HBT 之高頻小信號等效電路模型………………………….…………….34
4.1 簡介…………………………………………….…………………………..34
4.2 產生區等效電路…………………………………………………………...34
4.3 HBT 之小信號等效電路…………………………………………………..37
4.4 萃取含電感性崩潰網路之HBT 的小信號等效電路元素……………....43
4.5 HBT 之輸入端模型與驗證………………………………………………..48
4.6 HBT 之輸出端模型與驗證………………………………………………..52
第五章 HBT 於崩潰區之線性度隨溫度的相依性………………………………...56
5.1 簡介………………………………………………………………………...56
5.2 HBT 於電感性崩潰區之線性度計算方法…………………………….….56
5.3 常溫之HBT 之線性度量測與分析………………………………………61
5.4 變溫之HBT 的線性度分析…………………………………...………….68
第六章 結論與未來展望…………………………………………...……………….75
附錄…………………………………………………………………………………..77
A.1 含記憶效應之非線性電路在時域的求解………………………………..77
A.2 沃特拉級數………………………………………………………………..79
參考文獻……………………………………………………………………………..82

[1] S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
[2] A. Inoue, S. Nakatsuka, R. Hattori, and Y. Matsuda, "The maximum operating region in SiGe HBTs for RF power amplifiers," in Proc. IEEE MTT-S Int. Microw. Symp., 2002, pp. 1023-1026.
[3] Y. Sun, G. G. Fischer, and J. C. Scheytt, "A compact linear 60-GHz PA with 29.2% PAE operating at weak avalanche area in SiGe," IEEE Trans. Microw. Theory Techn., vol. 60, pp. 2581-2589, Aug. 2012.
[4] J. B. Steighner and J. S. Yuan, "The effect of SOA enhancement on device ruggedness under UIS for the LDMOSFET," IEEE Trans. Device Mater. Rel., vol. 11, pp. 254-262, Jun. 2011.
[5] S. Ganesan, E. Sanchez-Sinencio, and J. Silva-Martinez, "A highly linear low-noise amplifier," IEEE Trans. Microw. Theory Techn., vol. 54, pp. 4079-4085, Dec. 2006.
[6] C. I. Lee, Y. T. Lin, and W. C. Lin, "Investigation of linearity in the high electric field region for SiGe HBTs based on volterra series," IEEE Trans. Device Mater. Rel., vol. 14, pp. 1049-1055, Dec. 2014.
[7] J. Lee, W. Kim, Y. Kim, T. Rho, and B. Kim, "Intermodulation mechanism and linearization of AlGaAs/GaAs HBTs," IEEE Trans. Microw. Theory Techn., vol. 45, pp. 2065-2072, Dec. 1997.
[8] M. S. Shirokov, S. V. Cherepko, X. Du, J. C. M. Hwang, and D. A. Teeter, "Large-signal modeling and characterization of high-current effects in InGaP/GaAs HBTs," IEEE Trans. Microw. Theory Techn., vol. 50, pp. 1084-1094, Apr. 2002.
[9] S. A. Maas, B. L. Nelson, and D. L. Tait, "Intermodulation in heterojunction bipolar transistors," IEEE Trans. Microw. Theory Techn., vol. 40, pp. 442-448, Mar. 1992.
[10] J. D. Cressler, E. F. Crabbe, J. H. Comfort, J. Y. C. Sun, and J. M. C. Stork, "An epitaxial emitter-cap SiGe-base bipolar technology optimized for liquid-nitrogen temperature operation," IEEE Electron Device Lett., vol. 15, pp. 472-474, Nov. 1994.
[11] S. Pruvost, S. Delcourt, I. Telliez, M. Laurens, N. E. Bourzgui, F. Danneville, et al., "Microwave and noise performance of SiGe BiCMOS HBT under cryogenic temperatures," IEEE Electron Device Lett., vol. 26, pp. 105-108, Feb. 2005.
[12] M. Schetzen, The Volterra and Wiener Theories of Nonlinear Systems: New York: Wiley, 1980.
[13] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated Circuits. Norwell, MA: Kluwer, 1998.
[14] Y. Okuto and C. R. Crowell, "Threshold energy effect on avalanche breakdown voltage in semiconductor junctions," Solid State Electron., vol. 18, pp. 161-168, 1975.
[15] M. E. Elta and G. I. Haddad, "Mixed tunneling and avalanche mechanisms in p-n junctions and their effects on microwave transit-time devices," IEEE Trans. Electron Devices, vol. 25, pp. 694-702, Jun. 1978.
[16] P. Ashburn, SiGe Heterojunction Bipolar Transistors. England: John Wiley & Sons Ltd, 2003.
[17] W. N. Grant, "Electron and hole ionization rates in epitaxial silicon at high electric fields," Solid-State Electron., vol. 16, pp. 1189-1203, Oct. 1973.
[18] K. Sakui, T. Hasegawa, T. Fuse, S. Watanabe, K. Ohuchi, and F. Masuoka, "A new static memory cell based on the reverse base current effect of bipolar transistors," IEEE Trans. Electron Devices, vol. 36, pp. 1215-1217, Jun. 1989.
[19] G. Niu, J. D. Cressler, S. Zhang, U. Gogineni, and D. C. Ahlgren, "Measurement of collector-base junction avalanche multiplication effects in advanced UHV/CVD SiGe HBT's," IEEE Trans. Electron Devices, vol. 46, pp. 1007-1015, May 1999.
[20] G. Niu, J. D. Cressler, U. Gogineni, and D. L. Harame, "Collector-base junction avalanche multiplication effects in advanced UHV/CVD SiGe HBTs," IEEE Electron Device Lett., vol. 19, pp. 288-290, Aug. 1998.
[21] C. I. Lee, V. H. Ngo, and D. S. Pan, "New phenomena of mixed breakdown in silicon," phys. stat. sol., vol. 243, pp. R25-R27, Feb. 2006.
[22] M. H. Woods, W. C. Johnson, and M. A. Lampert, "Use of a Schottky barrier to measure impact ionization coefficients in semiconductors," Solid-State Electronics, vol. 16, pp. 381-394, 1973.
[23] D. A. Neamen, Semiconductor Physics and Devices: McGraw.Hill, 2003.
[24] G. N. J. D. Cressler, Silicon-Germanium Heterojunction Bipolar Transistors. Boston: ARTECH HOUSE, 2002.
[25] J. H. K. Vuolevi and T. Rahkonen, "Extraction of a nonlinear AC FET model using small-signal S-parameters," IEEE Trans. Microw. Theory Techn., vol. 50, pp. 1311-1315, May 2002.
[26] A. M. E. Safwat and L. Hayden, "Sensitivity analysis of calibration standards for fixed probe spacing on-wafer calibration techniques [vector network analyzers]," in IEEE MTT-S Int. Microwave Symp. Dig., 2002, pp. 2257-2260.
[27] C. I. Lee, V. H. Ngo, and D. S. Pan, "Inductance probing into the semiconductor breakdown," Appl. Phys. Lett., vol. 89, pp. 172112-172112-3, Oct. 2006.
[28] C. I. Lee, W. C. Lin, and Y. T. Lin, "Modeling inductive behavior of MOSFET scattering parameter S22 in the breakdown regime " IEEE Trans. Microw. Theory Techn., vol. 60, pp. 502-508, Mar. 2012.
[29] G. Qin, Y. Yan, N. Jiang, J. Ma, P. Ma, M. Racanelli, et al., "RF characteristics of proton radiated large-area SiGe HBTs at extreme temperatures," Microelectron. Reliabil., vol. 52, pp. 2568-2571, Nov. 2012.
[30] B. Li and S. Prasad, "Intermodulation analysis of the collector-up InGaAs/InAlAs/InP HBT using Volterra series," IEEE Trans. Microw. Theory Techn., vol. 46, pp. 1321-1323, Sep. 1998.
[31] C. Yu, J.-S. Yuan, and H. Yang, "MOSFET linearity performance degradation subject to drain and gate voltage stress," IEEE Trans. Device Mater. Rel., vol. 4, pp. 681-689, Dec. 2004.
[32] G. Sasso, M. Costagliola, and N. Rinaldi, "Avalanche multiplication and pinch-in models for simulating electrical instability effects in SiGe HBTs," Microelectron. Reliabil., vol. 50, pp. 1577-1580, Sep.–Nov. 2010.
[33] H. Wong, Y. Fu, J. J. Liou, and Y. Yue, "Hot-carrier reliability and breakdown characteristics of multi-finger RF MOS transistors," Microelectron. Reliabil., vol. 49, pp. 13-16, Jan. 2009.
[34] S. H. Voldman, "A review of latchup and electrostatic discharge (ESD) in BiCMOS RF silicon germanium technologies: Part I—ESD," Microelectron. Reliabil., vol. 45, pp. 323-340, Feb. 2005.
[35] A. Ahmed, S. S. Islam, and A. F. M. Anwar, "A temperature-dependent nonlinear analysis of GaN/AlGaN HEMTs using Volterra series," IEEE Trans. Microw. Theory Techn., vol. 49, pp. 1518-1524, Sep. 2001.
[36] A. Samelis and D. Pavlidis, "Mechanisms determining third order intermodulation distortion in AlGaAs/GaAs heterojunction bipolar transistors," IEEE Trans. Microw. Theory Techn., vol. 40, pp. 2374-2380, Dec. 1992.
[37] R. A. Minasian, "Intermodulation distortion analysis of MESFET amplifiers using the Volterra series representation," IEEE Trans. Microw. Theory Techn., vol. 28, pp. 1-8, Jan. 1980.
[38] J. S. Yuan and J. H. Ning, "Effect of impact ionization on CJC of heterojunction bipolar transistors," Solid-State Electronics, vol. 38, pp. 742-744, 1995.
[39] S. Jin, B. Park, K. Moon, M. Kwon, and B. Kim, "Linearization of CMOS Cascode Power Amplifiers Through Adaptive Bias Control," IEEE Transactions on Microwave Theory and Techniques, vol. 61, pp. 4534-4543, 2013.
[40] S. Boumaiza and F. M. Ghannouchi, "Thermal memory effects modeling and compensation in RF power amplifiers and predistortion linearizers," IEEE Trans. Microw. Theory Techn., vol. 51, pp. 2427-2433, 2003.
[41] K. J. Gan, C. S. Tsai, and D. S. Liang, "Design and characterization of the negative differential resistance circuits using the CMOS and BiCMOS process," Analog Integr. Circuits Signal Process., vol. 62, pp. 63-68, 2010.