在現今多核心處理器中，加入許多相同(同質架構)或不同(異質架構)的核心整合而成，為了有更好的晶片內網路，能夠提高傳輸效能，以及電路簡單容易實行。在網路內的路由器採用circuit-switched router的方式，而circuit switching 是以非同步電路來設計，電路簡單、容易去實行以及傳遞速度快，且不會有全域時脈（Global clock）所產生的問題，例如耗能、增加面積以及發生Clock skew的問題。在網路拓撲上，應用在環狀網路具有multi-transaction bus 架構，可以有多個核心同時進行存取，增加傳輸量。當核心數量增加時傳送距離變遠，因此利用環狀網路拓撲來應用在網狀網路拓撲降低傳送距離以提高傳輸效能。在仲裁器的方面使用分散式仲裁器，可以避免當中央式仲裁器在核心數目增加而導致中央仲裁電路變很複雜，所以會應用在分散式仲裁器的非同步環狀網路，而在分散式仲裁器，本論文會提出自我調整優先權SAP(self-adjusting priority)仲裁策略，傳送到網路上的封包，封包中擁有較高的封包權重稱為winner path相反的稱為loser path。當封包與封包發生碰撞時，winner path將較高的封包權重交給loser path而winner path則帶走較低的封包權重，因此在路由器內發生碰撞時透過交換封包權重的方式，來達到各個核心都有公平的傳輸機會，SAP仲裁策略只需要使用比較器以及簡單的交換電路用於分散式系統中，可以做到具有公平的仲裁機制、電路簡單、可擴充性、通用性以及低耗功的晶片內網路。

The multi-core systems are usually implemented on homogeneous or heterogeneous cores, in order to design the better NOC (network on chip), it must consider the performance, scalability, simplifies hardware design and arbitration strategy at the on chip network. The routers are designed with circuit-switched network, circuit switching is asynchronous circuits and routers have no queuing (buffering), therefore, it is simple and efficient in implementation. Synchronous circuit is network with a clock source, but the distributing global clock has many problems such as power consumption, increasing the area and Clock skew. Ring topology with multi-transaction bus architecture. It could make multiple packets to access the bus at the same time, so that the multi-transaction bus architecture is better to get more throughputs. When the number of cores increase, the central arbiter circuit is more complexity, this thesis presents an SAP (self-adjusting priority) schedule that can fairly adjust priorities of each component by appropriately exchanging weighting at distributed arbiter. When numerous requests encounter contention on a network, a winner owning the highest priority will exchange its priority with the lowest priority of these requests. This principle guarantees that winners will decreased the opportunity of incurring network at the next time. In opposition, these losers can obtain the higher priority than that of the original. Therefore, the proposed scheme not only offers fair strategy, but also simplifies hardware design.

摘要 i
ABSTRACT ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 簡介 1
1-1 研究動機 1
1-2 研究目的 2
1-3 論文架構 2
第二章 相關研究 3
2-1 Circuit Switching 以及Packet Switching 的比較 5
2-1.1 Circuit Switching 5
2-1.2 packet Switching 6
2-2 晶片上的互聯網絡 9
2-2.1 同步互連網絡 9
2-2.2 非同步互連網絡 16
2-3 仲裁策略 18
2-3.1 Fixed weight Arbitration 18
2-3.2 Aging-Based Arbitration 19
2-3.3 Long-Distance-first-execute Arbitration 20
2-3.4 Remaining-path Arbitration 21
2-4 整理和探討 22
第三章 公平仲裁策略的分散式非同步環狀網路之設計 23
3-1 SAP(self-adjusting priority) 仲裁策略 25
3-2 分散式非同步環狀匯流排架構 29
3-2.1 單向分散式非同步環狀匯流排架構 29
3-2.2 雙向分散式非同步環狀匯流排架構 35
3-3 SAP仲裁策略於環狀網路的工作流程 37
3-3.1 兩個封包碰撞情形 37
3-3.2 連續碰撞的情形 40
3-4 SAP 仲裁策略於網狀網路 45
3-4.1 分散式網狀網路匯流排架構 45
3-5 分散式環狀網路之應用 55
3-6 複合式sap仲裁策略 59
第四章 模擬結論與探討 60
4-1 模擬平台介紹 60
4-2 模擬結果與分析 60
4-2.1 單向環狀拓撲 60
4-2.2 雙向環狀拓撲 64
4-2.3 單向Torus拓撲 66
4-2.4 雙向Torus拓撲 68
4-2.5 Mesh拓撲 71
4-3 模擬結論 73
第五章 結論 74
參考文獻 75

[1] D. Wiklund and D. Liu, SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems, Proc. Int"l Parallel and Distributed Processing Symp. 2003, pp. 78-85, 2003.
[2] P. T. Wolkotte , G. J. Smit , G. K. Rauwerda and L. T. Smit "An energy efficient reconfigurable circuit-switched network-on-chip", Proc. Int. Parallel Distrib. Process. Symp., pp.155a 2005
[3] V. Rantala, T. Lehtonen and J. Plosila, Network on Chip Routing Algorithms, TUCS Technical Report, No 779, August 2006.
[4] Handbook, Cell Broadband Engine Programming Handbook , Version 1.1,IBM, published on 24 April 2007
[5] D. N. Jayasimha, B. Zafar, Y. Hoskote, “On-chip interconnection networks: why they are different and how to compare them,” Technical Report, Intel Corp., 2006.
[6] http://pages.cs.wisc.edu/~tvrdik/7/html/Section7.html
[7] A. Agarwal, C. Iskander, H. Multisystems, and R. Shankar, “Survey of network on chip (noc) architectures & contributions,” in Journal of Engineering, Computing and Architecture, 2009.
[8] D. Abts and D. Weisser. Age-based packet arbitration in large-radix k-ary n-cubes. In SC, 2007.
[9] L. Seiler, D. Carmean, E. Sprangle, T. Forsyth, M. Abrash, P. Dubey, S. Junkins, A. Lake, J. Sugerman, R. Cavin, R. Espasa, E. Grochowski, T. Juan, and P. Hanrahan. “Larrabee: a many-core x86 architecture for visual computing,” ACM Transactions on Graphics, 27(3):1–15, 2008.

[10] P. Cheolmin, R, Badea, L. Biro, J. Chang, T. Singh, J. Vash, W. Bo, T. Wang, “A 1.2 TB/s On-Chip Ring Interconnect for 45nm 8-Core Enterprise XeonR Processor,” IEEE ISSCC Digest of Technical Papers, pp. 180-181, 2010.
[11] M.M. Lee, J. Kim, D. Abts, M. Marty and J.W. Lee, "Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs," Micro, IEEE/ACM, pp.509-519, Dec. 2010
[12] R. Lu, A. Cao and C. Koh, "SAMBA-Bus : A High Performance Bus Architecture for System-on-Chips," IEEE Transaction on VLSI Systems, Vol.15, No.1, pp. 69-79, Jan. 2007.
[13] Mirza-Aghatabar, M.; Koohi, S.; Hessabi, S.; Pedram, M., "An Empirical Investigation of Mesh and Torus NoC Topologies Under Different Routing Algorithms and Traffic Models", Euromicro Conference on Digital System Design Architectures, Methods and Tools, Page(s):19-26, 2007.
[14] Kai-ming Yang, Kin-fong Lei, Jih-ching Chiu,” Design of an Asynchronous
Ring Bus Architecture for Multi-Core Systems” Computer Symposium (ICS), 2010 International ,16-18 Dec. 2010, 682 - 687

[15] A. Lines, “Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs”, Proceedings 11th Symposium on High Performance Interconnects, pp 2 – 9, Aug. 2003.
[16] A. T. Tran, D. N. Truong, B. M. Baas, “A Low-Cost High-Speed Source-Synchronous Interconnection Technique for GALS Chip Multiprocessors,” Circuits and Systems, 2009. ISCAS 2009. IEEE International Symposium on, pp. 996-999, May 2009.
[17] P. Liljeberg, J. Plosila, J. Isoaho, “Self-timed ring architecture for SoC pplications , ” Proc. SOC Conference, pp. 359-362, September 2003.
[18] AMBA Specification, ARM Ltd, Hall.
[19] Y. Thonnart , P. Vivet and F. Clermidy "A fully-asynchronous low-power framework for GALS NoC integration", Proc. Conf. DATE, pp.33 -38 2010
[20] A. Sheibanyrad , I. M. Panades and A. Greiner "Systematic comparison between the asynchronous and the multi-synchronous implementations of a network-on-chip architecture", Proc. Des., Autom. Test Eur. Conf., pp.1090 2007
[21] M. Ali , M. Welzl , A. Adnan and F. Nadeem "Using the NS-2 network simulator for evaluating network-on-chips (NoC)", Proc. IEEE 2nd Int. Conf. Emerging Technol., pp.506 2006
[22] mde, M., Felicijan, T., Edwards, A. E. D., and Lavagno, L. 2005. Asynchronous on-chip networks. IEE Proceedings of Computers and Digital Techniques 152, 273--283.