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博碩士論文 etd-0814117-172335 詳細資訊
Title page for etd-0814117-172335
論文名稱
Title
使用拔靴帶式開關控制轉導放大器快速鎖定之鎖相迴路設計
A Fast Locked Phase Locked Loop with a Bootstrapped Switch Controlled Operational Transconductor Amplifier
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
62
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-09-14
繳交日期
Date of Submission
2017-09-14
關鍵字
Keywords
相位頻率偵測器、電荷幫浦、鎖相迴路、壓控振盪器、拔靴帶式開關、可控式轉導放大器
PLL, Controllable OTA, VCO, Charge Pump, PFD, Bootstrapped Switch
統計
Statistics
本論文已被瀏覽 5667 次,被下載 57
The thesis/dissertation has been browsed 5667 times, has been downloaded 57 times.
中文摘要
本論文採用TSMC 90nm製程技術,在供應電壓1V下,提出了一個高調頻範圍與快速鎖定且除整數之頻率合成器。
此頻率合成器主要應用於IEEE 802.11ac Wi-Fi,提供4.243GHz至5.202GHz的本地振盪器。本論文所提出的頻率合成器包含相位頻率偵測器(Phase / Frequency Detector, PFD) 、低通迴路濾波器(Low Pass Filter, LPF)、電壓比較器(Comparator) 、可控式轉導放大器(Controllable Operational Transconductance Amplifier, C-OTA) 、電荷幫浦(Charge Pump, CP)、壓控振盪器(Voltage Control Oscillator, VCO)、拔靴帶式開關(Bootstrapped Switch)、非重疊電路(Non-overlapping Circuit)、上下計數器(Up/Down Counter)以及雙模計數器(Pulse-Swallow Counter)。
在此系統中,藉由比較V_ctrl,改變C-OTA的控制碼,以提升gm值和加大注入LPF之電流,進而達到快速鎖定之目的。
本論文提出之頻率合成器經模擬結果顯示功率消耗為9.48mW,鎖定時間為7.2μs,輸出頻率4.243GHz~5.202GHz。
Abstract
The proposed PLL in this thesis is implemented in TSMC 90nm 1P9M RF technology with a 1V supply voltage. This thesis presents a wide tuning and fast locking CMOS integer-N frequency synthesizer. The synthesizer is mainly used for IEEE 802.11ac unlicensed band of Wi-Fi (Wireless Fidelity). It provides one ration frequency ranged from 4.243GHz to 5.202GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer contains a Phase / Frequency Detector, a Low Pass Filter , Comparator, Controllable Operational Transconductance Amplifier, a Charge Pump, a Voltage Control Oscillator, Bootstrapped Switch, Non-overlapping Circuit, Up/Down Counter, and a Pulse-Swallow Divider.
In order to speed up the lock time, the synthesizer increased the value of gm and the current injection into the LPF by comparing the V_ctrl and change the digital control code of C-OTA.
The simulation result of the synthesizer is shown that the power dissipation is 9.48mW, the output frequency is 4.243GHz~5.202GHz, the lock time is 7.2μs.
目次 Table of Contents
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 viii
第1章 緒論 1
1.1 研究動機 1
1.2 論文組織 1
第2章 基本架構介紹 2
2.1 鎖相迴路基礎觀念 2
2.2 鎖相迴路基礎架構與操作原理 3
2.2-1 相位頻率偵測器(Phase Frequency Detector, PFD) 3
2.2-2 電荷幫浦(Charge Pump, CP) 5
2.2-3 迴路濾波器(Loop Filter) 6
2.2-4 壓控振盪器(Voltage Control Oscillator, VCO) 7
2.2-5 除頻器(Frequency Divider) 9
2.3 加速鎖定類型鎖相迴路介紹 10
2.3-1 使用連續時間相位頻率偵測器快速鎖定技術於鎖相迴路 10
2.3-2 使用雙斜率相位頻率偵測器與電荷幫浦快速鎖定鎖相迴路 12
第3章 目標架構電路分析及實現 13
3.1 架構簡介 13
3.2 相位頻率偵測器(Phase/Frequency Detector, PFD) 16
3.3 電荷幫浦(Charge Pump, CP) 18
3.4 迴路濾波器(Loop Filter, LF) 22
3.5 壓控震盪器(Voltage Control Oscillator, VCO) 25
3.6 拔靴帶式開關(Bootstrapped Switch) 27
3.7 除頻器(Divider) 30
3.8 可控式轉導放大器(Controllable OTA) 33
3.9 電壓比較器(Comparator) 35
3.10 上/下計數器(UP/DN Counter) 37
3.11 非重疊電路(Non-overlapping Circuit) 38
第4章 目標架構電路之模擬 39
4.1 簡介 39
4.2 鎖相迴路各子電路之模擬 39
4.2-1 相位頻率偵測器 39
4.2-2 電荷幫浦 41
4.2-3 壓控震盪器 41
4.2-4 可控式轉導放大器 43
4.2-5 拔靴帶式開關 43
4.2-6 電壓比較器 44
4.2-7 上/下計數器 44
4.3 鎖相迴路系統模擬 45
第5章 目標電路模擬效能 47
5.1 效能比較 47
第6章 結論與未來展望 48
6.1 結論 48
6.2 未來展望 49
參考文獻 50
參考文獻 References
[1] C.Y. Li, C.L. Lee, M.H. Hu, H. P. Chou, “A Fast Locking-in and Low Jitter PLL With a Process-Immune Locking-in Monitor,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), vol. 22, no. 10, pp. 2216-2220, Oct. 2014.
[2] 劉深淵、楊清淵, “鎖相迴路”, 滄海書局, 2006.
[3] F. Gardner, “Charge-pump phase-locked loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp.1849-1858, Nov. 1980.
[4] B. Razavi, “Design of analog CMOS integrated circuits,” McGraw-Hill Education, 2001.
[5] J. Rogers, C. Plett, F. Dai, “Integrated circuit design for high-speed frequency synthesis,” Artech House Publishers, 2006.
[6] Jun Pan, Tsutomu Yoshihara “A Fast Lock Phase-Locked Loop Using a Continuous-Time Phase Frequency Detector,” 2007 IEEE Conference Electron Devices and Solid-State Circuits(EDSSC), pp.393-396, Dec. 2007.
[7] Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying, “A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 11, pp.892-896, Nov. 2003.
[8] B. Lee, C. H. Jung, S. C. Park, S.W. Kim, “Fast-locking phase-error compensation technique in PLL,” 2012 IEEE International Conference Solid-State and Integrated Circuit Technology (ICSICT), pp.1-3, 29 Oct.-1 Nov. 2012.
[9] I.T. Lee, Y.T. Tsai, S. I. Liu, “A fast-locking phase-locked loop using CP control and gated VCO,” 2012 International Symposium VLSI Design Automation and Test (VLSI-DAT), pp.1-4, Apr. 2012.
[10] J. G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp.1723-1732, Nov. 1996.
[11] H.O. Johansson, “A simple precharged CMOS phase frequency detector,” IEEE Journal of Solid-State Circuits, vol. 33, no. 2, pp.295-299, Feb. 1998.
[12] J.-R. Yuan, C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal of Solid-State Circuits, vol. 24, no. 1, pp.62-70, Feb. 1989.
[13] J.-R. Yuan, C. Svensson, “Fast CMOS nonbinary divider and counter,” Electronics Letters, vol. 29, no. 13, pp.1222-1223, June 1993.
[14] Jian-bin Pan, Yuan-fu Zhao, Xin Liang, “A high-performance CMOS charge pump for PLLs,” 2009 International Conference on Microelectronics(ICM), pp.98-101, Dec. 2009.
[15] W. Rhee, “Design of high-performance CMOS charge pumps in phase-locked loops,” 1999 IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp.545-548, 30 May-2 June 1999.
[16] Tsung-Hsien Lin, Ching-Lung Ti, Yao-Hong Liu, “Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp.877-885, May 2009.
[17] B. Razavi, “RF microelectronics,” Prentice Hall, 2011.
[18] Lin Jia, A. Cabuk, Jian-Guo Ma, Kiat Seng Yeo, Manh Anh Do, “A 52 GHz VCO with low phase noise implemented in SiGe BiCMOS technology, ”The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, pp.264-269, July 2003.
[19] C. Lam, B. Razavi, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-/spl mu/m CMOS technology,” 1999 Symposium on VLSI Circuits. Digest of Papers, pp.117-120, June 1999.
[20] Bhaba Priyo Das, Neville Watson, Yonghe Liu, “Electronically tunable PLL controller design using OTA,” 2010 IEEE International Conference on Electronics Circuits and Systems (ICECS), pp.198-202, Dec. 2010.
[21] R. Jacob Baker, “CMOS Circuit Design, Layout and Simulation,” Wiley-IEEE Press, 2010.
[22] Yao-Chian Lin, Mei-Ling Yeh, Chung-Cheng Chang, “A high figure-of-merit low phase noise 15-GHz cmos VCO,” Journal of Marine Science and Technology, vol. 21, no. 1, pp. 82-86, 2013.
[23] Mezyad Amourah, Morgan Whately, “A novel switched-capacitor-filter based low-area and fast-locking PLL,” 2015 IEEE Custom Integrated Circuits Conference (CICC), pp.1-6, Sep. 2015.
[24] Fatima T. Almutairi, Reem T. Almutairi, “Fast-lock phase-locked loop with adaptive controller in 0.18-μm CMOS,” 2016 International Conference on Electronic Devices Systems and Applications (ICEDSA), pp.1-5, Dec. 2016
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