本論文提出一個操作在供應電壓 1.2V、解析位元 10 位元、每秒取樣兩億五 千萬次之二元搜尋式及一次轉換兩位元制具容錯能力雙通道連續漸進式類比數位轉換器，採用 TSMC 90 奈米 製程技術，可應用於無線通訊系統前端晶片接收端。
將ADC分為兩級，第一級使用二元搜尋式類比數位轉換器，藉以達到高速，但是比較器會隨者解析度的增加而功率消耗越大，所以第一級設定解析5位元，而第二級使用雙通道7位元一次兩位元轉換的連續漸進式類比數位轉換器，利用一次兩位元轉換的連續漸進式類比數位轉換器的速度提升，再加上雙通道的速度加乘，理論上可以跟二元搜尋式類比數位一樣快，這樣即使使用Two Stage也不會被拖慢，以達到高速、高解析的效果，以及新型電容陣列，可以利用在一次兩位元連續漸近式類比數位轉換器中的數位類比轉換，達到容錯的機制，並且可以有效降低功耗，無須外接校正電路。

In this thesis, a 10-bit binary search assisted two channel SAR ADC with a two bit per conversion and error tolerance ability operating in 250Ms/s sampling rate with 1.2 supply voltage is presented. The ADC adopt TSMC 90nm process and can be used for receiving in front-end chip of wireless communication system.
The ADC is divided into two stages, the first level using binary search ADC, in order to achieve high-speed. But the comparator will increase the power consumption as the resolution increases, so the first stage is set to resolve 5 bits. The second srage uses a two-channel 7-bit two-bit conversion of SAR ADC. With a two-bit conversion SAR ADC to speed up, coupled with the dual-channel speed multiplication, in theory, it can be as fast as the binary search ADC. So that even with the Two Stage can also achieve high-speed, high-resolution results. The new capacitor array can be used in a two-bit SAR ADC to achieve fault tolerance mechanisms, and can reduce power consumption effectively without external correction circuit

中文摘要 i
Abstract ii
目錄 iii
圖目錄 vi
表目錄 viii
Chapter1 緒論 1
1.1 研究動機與目標 1
1.2 論文章節組織 2
Chapter2 基本架構與原理介紹 3
2.1 介紹 3
2.2 類比數位轉換器的參數考量 3
2.2.1 靜態性能(Static Performance) 3
2.2.2 動態效能(Dynamic Performance) 6
2.3 類比數位轉換器架構 7
2.3.1 快閃式類比數位轉換器（ Flash ADC） 7
2.3.2 二元搜尋式類比數位轉換器(Binary Search ADC) 8
2.3.3 管線式類比數位轉換器(The Pipeline ADC) 9
2.3.4 連續漸進式類比數位轉換器(SuccessiveApproximationADC) 10
2.3.5 分行並行式類比數位轉換器(Time Interleaved Parallel ADC) 12
Chapter3 目標架構電路介紹與分析 14
3.1 介紹 14
3.2 取樣保持電路 14
3.3 導通電阻設計 15
3.4 MOS開關 16
3.4.1 CMOS開關 16
3.4.2 電荷注入效應(Charge Injection) 17
3.4.3 時脈耦合效應(Clock Feedthrough) 18
Chapter4 目標類比數位轉換器設計 20
4.1 整體架構 20
4.2 第一級二元搜尋式ADC 22
4.3 第二級一次轉換兩位元與非二進制具容錯能力雙通道SAR ADC 24
4.3.1 一次轉換二位元連續漸進式(SAR) ADC 24
4.3.2 拔靴帶式開關(Bootstrapped Switch) 26
4.3.3 動態比較器 28
4.3.4 單調式電容陣列 30
4.3.5 非二進制權重電容陣列 32
4.3.6 比較器與控制電路邏輯 36
4.3.7 一次轉換兩位元之切換方式 37
4.3.8 參考電壓電容陣列（VREF capacitor array） 37
4.3.9 非同步SAR控制電路 38
4.4 解碼器 40
4.5 非重疊時脈產生器 42
Chapter5 效能與模擬結果分析 43
5.1 效能測試方法 43
5.2 FFT test 44
5.3 模擬結果與比較 45
5.3.1 靜態分析 45
5.3.2 動態分析 48
Chapter6 結論與未來展望 52
6.1 結論 52
6.2 未來展望 53
Reference 54

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