本篇論文研究的方向為降低HomePlug AV電力線通訊系統因傳輸時的雜訊干擾造成的解碼錯誤機率，使用Matlab/Simulink建立系統架構並藉由此架構模擬傳輸運作與效能分析。 HomePlug AV系統標準規格共包含Scramble、Turbo Code、Interleaver、QAM、FFT、Preamble等元件，其中使用Turbo Code來進行錯誤碼更正，其編碼率為1/2，並選擇Log-MAP演算法來進行解碼，再利用1024 QAM來調變子載波，最後經由3072點快速傅立葉轉換來產生輸出訊號，同步機制使用Preamble來傳遞同步訊號，並透過Timing Recover演算法來檢測是否有封包的傳入。
本論文之HomePlug AV系統架構，使用國家晶片中心提供之TN90GUTM製程完成設計，傳送端與接收端的面積分別為833,142 μm2與1,625,788 μm2，最高資料傳送速率可達139.46Mbps，可滿足高品質數位家庭影音系統之需求，並具有較高的抗噪表現，來降低使用環境所造成的干擾，且電路架構已經過國家晶片中心Cell-Base Design Flow驗證，確保其效能與功能正確無誤。

This thesis implements the HomePlug AV power line communication system to reduce the probability of decoding errors caused by noise interference during transmission. The architecture of HomePlug AV system includes Scramble, Turbo Code, Interleaver, QAM, FFT, Preamble, etc. Turbo Code is used to perform error correction and the code rate is 1/2. Log-Max Posterior Probability (Log-MAP) is used to decode the Turbo Code. QAM-1024 is applied to the modulated subcarrier. Finally, the fast Fourier transform (FFT) generates the transmitted data to the power line. The Preamble is used as transmitting synchronous signals. The timing recover algorithm will detect whether there is an incoming packet.
The HomePlug AV system uses the Chip Implementation Center TN90GUTM process to implement the design. The area of transmission part and receiving part is 833,142 μm2 and 1,625,788 μm2. The maximum data transfer rate is 139.46 Mbps which can satisfy the High-quality digital home audio system. The circuit architecture has passed the Chip Implementation Center Cell-Base Design Flow Verification.

目錄
第1章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第2章 通訊系統介紹 3
2.1 單載波與多載波的傳輸方式 3
2.2 正交分頻多工的調變方式 5
2.3 HomePlug AV規格介紹 6
第3章 HomePlug AV系統架構規劃 9
3.1 Scrambler/Descrambler 9
3.2 Turbo Encoder 9
3.3 Turbo Decoder 12
3.4 Interleaver/DeInterleaver 19
3.5 QAM/DeQAM 21
3.6 IFFT/FFT 22
3.7 Preamble / Timing Recover 30
3.8 Cyclic Prefix 31
3.9 系統工作頻率 32
第4章 HomePlug AV系統架構實現 33
4.1 Scrambler / DeScrambler架構實現 33
4.2 Turbo Encoder架構實現 34
4.3 Turbo Decoder架構實現 36
4.3-1 分支路就計算器-BMC 36
4.3-2 前向狀態處理器-FP 37
4.3-3 後向狀態處理器-BP 41
4.3-4 軟式輸出計算器-SOC 42
4.3-5 SW-Log-MAP架構 44
4.4 Interleaver/ DeInterleaver架構實現 47
4.5 QAM-1024/ DeQAM-1024架構實現 49
4.6 IFFT-3072架構實現 51
4.7 FFT-3072架構實現 60
4.8 Preamble架構實現 62
4.9 Timing Recover架構實現 63
4.10 HomePlug AV系統架構整合 64
第5章 HomePlug AV系統模擬及驗證 66
5.1 Scramble/Descramble 驗證及模擬 67
5.2 Turbo Encoder/Turbo Decoder模擬及驗證 68
5.3 Interleaver/DeInterleaver模擬及驗證 69
5.4 QAM/DeQAM模擬及驗證 70
5.5 IFFT/FFT模擬及驗證 72
5.6 Preamble/Timing Recover模擬及驗證 73
5.7 HomePlug AV系統模擬與驗證 75
5.8 HomePlug AV系統實現規格 77
第6章 結論 79
第7章 參考文獻 80

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