本篇論文採用Electronic System Level (ESL) 設計方法，實踐了部分ESL設計流程，所使用的是CoWare ESL工具 – ConvergenSC。略過ESL設計流程中的演算法設計與分析、資料流的分析，著重的部分有三項。一為基本元件的建立，主要是SystemC抽象化模組的設計與精鍊，採用Transaction Level Modeling (TLM)的方法進行模組的抽象化，使用的是System Level Language – SystemC。一為系統平台的建立，使用ESL工具快速地建立不同架構的系統平台，主要著重於AMAB-Based的系統平台。另一為系統架構的探討、分析與改進，透過模擬後所產生的資料，分析數據所代表的意義並進行架構的改進。我們提供了一個MP3 Decoder的實際範例，從程式的切割到建立系統平台，並進行記憶體配置、硬體加速器的使用、硬體加速器介面、系統匯流排架構以及管線化排程對效能的影響；最後則選擇了部分架構進行面積與能量消耗的分析。

This thesis investigates Electronic System Level (ESL) design flow by implementing some applications using CoWare ESL tool, ConvergenSC. There are three focuses in this thesis: basic cell modeling, system platform design, and system level architecture exploration. In the basic cell modeling, we adopt the system level language, SystemC, to describe the abstract behavior of various modules in Transaction Level Modeling (TLM). In system platform design, we use the ESL tool to create system platforms of different architectures, mainly AMBA-based system platforms. In the system architecture exploration, we analyze the simulation results in different system platform architectures and present several strategies (memory allocation, ASIC design, DMA, Pipeline Scheduling) to improve the overall system performance in the application example of MP3 decoder. The rough estimation of power and area is also included in the system architecture exploration stage.

Chapter 1 論文簡介 1
1.1 動機 1
1.2 主要貢獻 1
1.3 論文架構 2
Chapter 2 背景與相關研究 3
2.1 背景 3
2.1.1 Electronic System Level Design 3
2.1.2 Transaction-Level Modeling 7
2.1.3 System Level Language: SystemC 10
2.1.4 Electronic System Level Tools Overview 15
2.2 相關研究 21
Chapter 3 Design Library 25
3.1 模組分類 25
3.1.1 以功能分類 25
3.1.2 以來源分類 26
3.1.3 以匯流排定位分類 27
3.1.4 以時間精確度分類 27
3.2 模組列表 28
3.2.1 CoWare Library 28
3.2.2 System Library 30
3.2.3 Memory Library 31
3.2.4 3D Library 32
3.2.5 DSP Library 34
3.2.6 MP3 Library 34
3.2.7 Peripheral Library 35
3.2.8 Monitor Library 36
3.3 SystemC Module Modeling 36
3.3.1 From Specification 36
3.3.2 From Application 39
3.3.3 From Reference Model 42
3.3.4 From Implementation Model 47
Chapter 4 System Level Architecture Exploration 48
4.1 System Architecture Exploration 48
4.1.1 Architecture Synthesis 48
4.1.2 Architecture Exploration 49
4.2 Case Study – MP3 50
4.2.1 MP3簡介 50
4.2.2 程式流程說明 51
4.2.3 系統架構探討及效能分析 52
4.2.4 系統架構與綜合分析 62
Chapter 5 結論與未來展望 72
5.1 結論 72
5.2 未來展望 72
參考文獻(References) 75
Appendix SystemC Pseudo Codes 78
A. Geometry Engine with Static Execution Time 78
B. Geometry Engine with Tile Divider 80
C. Adsp218x 83
D. Simple Memory 85
E. Resetable Memory 86
F. AHB Bus Monitor 87
G. Synthesis Filter Bank ASIC (Slave Interface) 88
H. Synthesis Filter Bank ASIC (Master/Slave Interface) 89
I. Output Device 91
J. AHB Interrupt Controller 92
K. APB Interrupt Controller 93
L. Clock Controller 94

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