隨著晶片系統設計複雜度的增加，高性能嵌入式記憶體核心所佔面積比重越來越多，至今嵌入式的記憶體儼然成為系統設計上最為需要考量的一部份。本論文實做一記憶體產生器，以減少記憶體在開發時的複雜度，讓使用者能快速整合適合的記憶體到設計中。論文中除了介紹記憶體各部分元件外，並採用了一省電的架構，將龐大的記憶體陣列切分區塊後分塊動作，並且利用多重電壓來對記憶體細胞元充電來減少功率的消耗，以符合日趨重要的功率消耗問題。另外，目前的多媒體系統皆需要大量的資料傳輸而為了達到壓縮及轉換的目的，也因為大量的資料必須傳入與運算，所以一個有效率的資料搬移方式就顯得相當的重要，我們在此論文中分別針對DCT、JPEG2000與3D圖學上的應用，提出數種不同存取方式的記憶體，以增加記憶體在多媒體應用存取上的效率。最後，我們的記憶體產生器可以根據使用者需要來產生記憶體模組或是抽換記憶體電路元件，此產生器包含了Behavior Model、Synopsys library、LEF File、Spice Netlist以及Layout，讓使用者在Cell-based流程可以完整並快速地完成。

As the complexity of SoC increases rapidly, embedded memory becomes one of the critical components in current SoC design. In this thesis, we develop a memory generator so that users can easily integrate proper embedded memory circuits into SoC chips. The generator is based on a low-power multi-voltage-source memory architecture that partitions the complete memory into two parts to avoid unnecessary operations. In addition, we also address the modification of the memory architectures in order to provide more efficient data accessing in multimedia applications such as DCT, JPEG-2000 and 3D graphics. The developed memory generator can produce all the necessary files required in the traditional cell-based design flow, including behavior model, Synopsys library, LEF file, Spice netlists and layouts, so that the designers can easily utilize the generated memory units in their ASIC designs.

CHAPTER 1. 導論
1.1 研究動機
1.2 論文組織
CHAPTER 2. 相關研究
2.1 記憶體產生器
2.2 記憶體架構
2.3 記憶體產生器的優點
CHAPTER 3. 記憶體產生器之設計
3.1 記憶體電路元件設計
3.1.1 記憶體細胞元設計
3.1.2 記憶體行、列解碼器設計
3.1.3 記憶體預先充電電路設計
3.1.4 寫入控制器與放大器電路設計
3.2 記憶體架構設計與實驗數據
3.2.1 記憶體架構設計
3.2.2 實驗數據
CHAPTER 4. 記憶體產生器之流程
4.1 產生器提供的模組
4.1.1 Behavior Model
4.1.2 Synopsys Timing Library
4.1.3 LEF Model
4.1.4 SPICE Netlist
4.1.5 Physical Layout
4.2 產生器的參數化及電路的取代
4.2.1 產生器的介面與使用
4.2.2 產生器在Layout上的限制
CHAPTER 5. 應用導向記憶體設計
5.1 MEMORY 3D 概念
5.1.1 Memory 3D 在 2D-DCT 上的應用
5.1.2 Memory 3D 在 JPEG 2000 上的應用
5.1.3 Memory 3D 在電路架構上的設計
5.2 3D 圖學記憶體
5.3 合成應用導向記憶體時，產生器所需之修改
CHAPTER 6. 記憶體產生器應用實例
CHAPTER 7. 未來展望
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