對於三維圖形應用程式的加速，實作三維圖形硬體加速器是最常解決加速的方法。本論文著重的目是基於實作的三維硬體加速器，探討三維圖形資料在記憶體配置情況以及三維繪圖系統晶片的不同匯流排架構，對系統效能的影響，並尋求三維圖形資料在三維圖形應用平台的最佳化配置方法，即可透過現有的硬體資源有效地改善整體應用系統的效能。為了達到目的，採用系統層級的模擬來觀察和分析硬體加速器對系統存取的行為，找出改善效能的關鍵。本文採用電子系統層級設計的方法來幫助系統模擬的行為，除了模擬時間比RTL層級快上好幾倍之外，抽象化的層級可以讓我們更容易描述和分析。在分析三維圖形資料在記憶體配置情況方面，我們觀察三維硬體加速器的資料結構對同步動態記憶體的影響，以減少存取同步動態記憶體的延遲時間為主，來決定資料分配的位置，所以切割資料並個別存放到不同的banks of SDRAM, scratch memory of system, built-in memory of hardware是有效的方法。在系統匯流排上，除了利用多層匯流排架構加大匯流排的頻寬之外，還以軟體改善方式加大存取的單位容量來改善系統效能。經過實驗模擬，本文將原本的三維硬體架構提升了百分之六十二的效能。

Hardware implementation is one of common solutions for accelerating 3D Graphics Pipelining Application. In this thesis, our purpose is to probe into the effect of 3D graphics system performance, according to the memory allocation of 3D graphics data and bus architecture for 3D graphics system-on-chip. And we also improve performance of whole application system efficiently by existent hardware resource. For getting the purpose, we use system level of simulation to observe and analyze the access of hardware accelerator in system and find out the key for improving performance. In this paper, we use ESL design to aid us for system simulation. Besides simulation time is much faster than RTL, abstract description is easy to implement and analyze. In memory organization, we must understand the relation of access data of 3D hardware with SDRAM, and reallocation memory. So, we divide each data and put them in different banks of SDRAM, scratch memory of system and built-in memory of hardware. Besides we increase the bandwidth of system bus by using multilayer architecture in system bus, we modify software to up the access times for improving performance. The experiment results point out that we speed up performance for 1.62 times.

Chapter 1. Introduction 1
1. 1 Background 1
1. 2 Motivation 2
1. 3 My Research 2
1. 4 Contribution 3
1. 5 Organization 3
Chapter 2. Related Work 4
2. 1 A Virtual Platform for Software Optimization 4
2. 2 Optimizing SoC Platform Architecture 6
Chapter 3. Introduction to NSYSU 3D Graphics SoC 9
3. 1 Background 9
3. 2 NSYSU Geometry-Engine 10
3. 2. 1 Function Description of Geometry-Engine 10
3. 2. 2 Hardware Design of Geometry-Engine 10
3. 2. 3 Data Type of Each Buffer 13
3. 3 NSYSU Rendering-Engine 13
3. 3. 1 Function Description of Rendering-Engine 13
3. 3. 2 Hardware Design of Rendering-Engine 14
3. 3. 3 Data Type of Each Buffer 18
3. 4 Tile-Based Rendering & Tile-list Buffer 18
Chapter 4. Analysis Platform 23
4. 1 SystemC Based Analysis Platform 23
4. 2 The Development of SystemC Environment 24
4. 3 CoWare－AMBA2.0 Library TLM API 26
4. 3. 1 Signals vs. Transfers 26
4. 3. 2 The time relation between Transfers and Signals 28
4. 4 SDRAM Controller Design for AHB Bus 30
4. 4. 1 Basic SDRAM Commands [14] 30
4. 4. 2 Write Command of SDRAM Controller Design 31
4. 4. 3 Read Command of SDRAM Controller Design 33
4. 5 3D Graphics Hardware－RTL to SystemC TLM 34
4. 5. 1 Untimed TLM Models 34
4. 5. 2 Untimed TLM Models plus Time Information 37
4. 5. 3 Improve Ineffective Wrapper Design 40
4. 6 Other IP Models 43
4. 7 Performance of 3D Application for System Platform 43
Chapter 5. Exploration of Memory Organization 47
5. 1 Simple Memory Allocation 47
5. 2 Tile-List Buffer Reallocation 48
5. 3 Experiment Results 50
5. 3. 1 Simple Memory Allocation 50
5. 3. 2 Tile-List Data Reallocation 51
Chapter 6. Exploration of On-chip Bus Organization 52
6. 1 Two-Layer AHB Architecture 52
6. 2 Multi-Layer AHB Architecture 53
6. 3 Experiment Results 54
6. 3. 1 Two-Layer AHB Architecture 54
6. 3. 2 Multi-Layer AHB Architecture 54
Chapter 7. Conclusions 57
Appendix A. Electronic System Level 63
Appendix A.1 Electronic System Level 65
Appendix A.2 Transaction Level Modeling 67
Appendix A.3 SystemC Based TLM 72
Appendix A.3.1 OSCI 73
Appendix A.3.2 OCP-IP 74
Appendix A.3.3 SystemC TLM for Bus Protocol 75
Appendix A.4 Electronic System Level Tools Overview 79
Appendix B. Overview of 3D Graphics 87
Appendix B.1 Function of 3D Graphics Pipelining 87
Appendix B.2 Function Description of Geometry Subsystem 87
Appendix B.2.1 Model View Transformation 88
Appendix B.2.2 Projection Transformation 90
Appendix B.2.3 Perspective Division 90
Appendix B.2.4 Viewport Transformation 91
Appendix B.2.5 Lighting and Shading Mode 91
Appendix B.2.6 Culling and Clipping 94
Appendix B.2.7 Setup 94
Appendix B.3 Rendering Function Description 94
Appendix B.3.1 Rasterization 95
Appendix B.3.2 Fragment processing 96

[1] Makoto Awaga, Tatsushi Ohtsuka, Hideki Yoshizawa, Shigeru Sasaki “3D Graphics Processor Chip Set” Proceedings of IEEE Micro, volume 15, issue 6 on page 37-45, December 1995.
[2] Ruei-Ting Gu, Tse-Chen Yeh, Wei-Sheng Hunag, Ting-Yun Huang, Chung-Hua Tsai Chung-Nan Lee, Ming-Chao Chiang, Shen-Fu Hsiao, Yun-Nan Chang, Ing-Jer Huang “A Low Cost Tile-based 3D Graphics Full Pipeline with Real-time Performance Monitoring Support for OpenGL ES in Consumer Electronics” Proceedings of IEEE International Symposium on Consumer Electronics, 2007. ISCE 2007.
[3] Henry Fuchs, John Poulton, John Eyles, Trey Greer, Jack Goldfeather, David Ellsworth, Steve Molnar, Greg Turk, Brice Tebbs, Laura Israel, “Pixel-planes 5: a heterogeneous multiprocessor graphics system using processor-enhanced memories” Proceedings of the 16th annual conference on Computer graphics and interactive technique.
[4] Milton Chen, Gordon Stoll, Homan Igehy, Kekoa Proudfoot, Pat Hanrahan “Simple models of the impact of overlap in bucket rendering” Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware.
[5] Hajime Kubosawa, Naoshi Higaki, Hiromasa Takahashi, “Four-way VLIW Geometry Processor for 3D Graphics Applications” FUJITSU SCIENTIFIC & TECHNICAL JOURNAL fascicolo1, volume36, page39 – 47, anno2000.
[6] Jaewan Bae, Donghyun Kim, and Lee-Sup Kim, ”An 11M-Triangles/sec 3D Graphics Clipping Engine for Triangle Primitives,” Proceedings of IEEE International Symposium on Circuits and Systems, vol. 5, pp. 4570 - 4573, May 2005.
[7] Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha “Scene Management Models and Overlap Tests for Tile-Based Rendering” Proceedings of the Digital System Design, Euromicro Symposium, 2004. DSD 2004.
[8] Edward Angel “Interactive Computer Graphics – A Top-Down Approach Using OpenGL, Fourth Edition” Addison Wesley.
[9] CoWare, Inc. “Developing Transaction-level Models in SystemC”, Available at http://www.coware.com/PDF/COWARETLMWHITEPAPER-AUG04.PDF.
[10] Lukai Cai and Daniel Gajski, “Transaction Level Modeling : An Overview”, Center for Embedded Comput. Syst., California Univ Irvine, CA, USA.
[11] OSCI TLM Working Group, “Transaction Level Modeling in SystemC”, Available at http://www.systemc.org/.
[12] OSCI, “SystemC 2.0 User’s Guide” Available at http://www.systemc.org/.
[13] Ning-Yaun Ker, Chung-Ho Chen “An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems” Proceedings of the ASP-DAC 2003 Design Automation Conference, 2003. Asia and South Pacific.
[14] Micron Technology, Inc. “SDRAM Technical Notes”, Available at http://www.micron.com/
[15] ARM, Inc. “PrimeCell® DMA Controller (PL330) Technical Reference Manual”, Available at http://www.arm.com/
[16] Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, “Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study”, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, Seoul, Korea.
[17] OCP-IP, “Open Core Protocol Specification”, Available at http://www.ocpip.org/
[18] Lukai Cai and Daniel Gajski, “Transaction Level Modeling in System Level Design”, Technical Report 03-10, Center for Embedded Computer Systems, University of California Irvine, 2003.
[19] Brian Bailey, Grant Martin, Andrew Piziali, “ESL Design And Verification”, Morgan Kaufmann, 2007.
[20] Lukai Cai and Daniel Gajski, “Transaction Level Modeling : An Overview”, Center for Embedded Comput. Syst., California Univ Irvine, CA, USA.
[21] David Maliniak, “SystemC Closes The C-To-RTL Gap”, OSCI/OCP-IP Special Report/Supplement to Electronic. Design, 13 Jan. 2005
[22] CoWare, Inc. “CoWare Platform Architect” http://www.coware.com/products/platformarchitect.php
[23] RealView CREATE Family, ARM, Inc. http://www.arm.com/products/DevTools/RealViewCREATE_Family.html
[24] International Business Strategies, Inc. Available at http://www.international-businessstrategies.com/.
[25] Object Management Group, “Unified Modeling Language“, Available at http://www.omg.org/.
[26] “SystemC促使SoC設計走向更高抽象層”, Available at http://www.eettaiwan.com/ ART_8800380422_480102_NT_1d2aa797.HTM
[27] Anssi Haverinen, Nokia, Maxime Leclercq, Texas Instruments, Norman Weyrich, Synopsys, Drew Wingard, Sonics, “SystemC based SoC Communication Modeling for the OCP Protocol”, White Paper V1.0 - October 14, 2002
[28] Mentor Graphics, Inc. Visual Elite, http://www.mentor.com/
[29] Cadence, Inc. Cadence Incisive, http://www.cadence.com/products/sd/Pages/default.aspx
[30] Synopsys, Inc. Discovery Verification Platform, http://www.synopsys.com/products/solutions/discovery_platform.html
[31] MathWork, Inc. MathWork Product, http://www.mathworks.com/products/product_listing/index.html
[32] EDA-ESL & SDA WALLCHART 2007, Available at http://www.garysmithEDA.com/
[33] C. J. Choi, G. H. Park, J. H. Lee, W. C. Park, T. D. Han “Performance Comparison of Various Cache Systems for Texture Mapping” Proceedings of International Conference on Power Electronics and Drives Systems, 2005. PEDS 2005.
[34] Michael Cox, Narendra Bhandari, Michael Shantz, “Multi-Level Texture Caching for 3D Graphics Hardware” Proceedings of The 25th Annual International Symposium on Computer Architecture, 1998.
[35] Mark Burton, James Aldis, Robert Günzel, Wolfgang Klingauf, “Transaction Level Modeling: A reflection on what TLM is and how TLM may be classified”, Specification & Design Languages (FDL), Barcelona, September 2007.
[36] Lei Tang, Yanhui Yang, Shaojun Wei, “Optimizing SoC Platform Architecture for Multimedia Applications”, Proceedings of 6th International Conference On ASIC(ASICON), 2005.
[37] Sungpack Hong, Sungjoo Yoo, Sheayun Lee, Sangwoo Lee, Hye Jeong Nam, Bum-Seok Yoo, Jaehyung Hwang, Donghyun Song, Janghwan Kim, Jeongeun Kim, HoonSang Jin, Kyu-Myung Choi, Jeong-Taek Kong, Soo-Kwan Eo, “Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study”, Proceedings of the 4th international conference on Hardware/software codesign and system synthesis, Seoul, Korea.
[38] Michael Cox, Narendra Bhandari, Michael Shantz, “Multi-Level Texture Caching for 3D Graphics Hardware” Proceedings of The 25th Annual International Symposium on Computer Architecture, 1998.