本論文包含兩個主題：一次植入式之脊椎電刺激（Spinal cord stimulation, SCS）系統晶片，以及高速耦合電容電路之設計。

第一個主題探討一可經由體外端線圈感應供電，並採用鋰電池儲存多餘電荷以供應體內裝置電源，且同時利用線圈達到體內外雙向溝通的脊椎電刺激系統晶片。該晶片具有可同時調整四組電極刺激樣式，並具有多模式來控制系統，大幅增進設定刺激樣式的靈活度，以及在非刺激期間低功率之需求。SCS晶片為體內刺激產生器之核心電路，其中包含一新式ASK（Amplitude-shift keying）解調變器可提供體內基頻電路穩定之解調訊號，使醫護人員對體內刺激波形之資料設定更為可靠。本設計使用TSMC 1P6M 0.18 μm 製程，製作出僅 1.71 × 1.41 mm2 之晶片面積，而藉此實作出的SCS體內刺激產生器也可控制於 24 cm3 以下，平均功率也僅 59.4 mW。

第二個主題探討一高速耦合電容電路之設計，利用此架構可使晶片間數位訊號以電容耦合方式傳接，並藉由將傳接電路埋設置耦合電容下端，進而縮減傳接模組面積。該電路在晶圓封裝量測上與3D積體電路之訊號傳輸上有十分前瞻之應用，本電路採用TSMC 1P6M 0.18 μm製程實作，具備可高達2 Gbps之傳輸速率，面積為1045 × 894 μm2，同時功耗也僅只有21.47 mW，在未來積體電路領域之可測試性設計應用方面深具潛力。

The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system （SCS）, and the design of an inter-chip capacitance coupling circuit.
In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-μm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW.
In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 μm 1P6M CMOS process. The chip area is 1045 × 894 μm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.

致謝 iv
摘要 v
Abstract vi
目錄 vii
圖次 ix
表次 xi
第一章 概論 1
1.1 前言 1
1.2 相關文獻與研究探討 3
1.2.1 一次植入式之脊椎電刺激系統晶片 3
1.2.2 高速電容耦合電路設計 5
1.3 研究動機 9
1.4 論文大綱 9
第二章 一次植入式之脊椎電刺激系統晶片 10
2.1 簡介 10
2.2 電路架構 10
2.3 電路設計 14
2.3.1 ASK解調變器 14
2.3.2 基頻電路 17
2.3.3 Reset訊號產生器 20
2.3.4 時脈產生器 21
2.3.5 電流式數位類比轉換器 22
2.3.6 電池電壓偵測電路 24
2.3.7 低壓降線性穩壓器 25
2.3.8 LSK調變器 28
2.3.9 刺激波形產生器 28
2.3.10 電池充電模組與電源管理 28
2.4 預計規格與效能比較 29
2.5 晶片佈局 30
2.5.1 佈局平面圖 30
2.5.2 佈局考量 31
2.6 晶片量測 32
2.6.1 晶片實作與量測結果 32
第三章 高速耦合電容電路設計 37
3.1 簡介 37
3.2 電路架構 37
3.2.1 單端時脈電路 38
3.2.2 雙端訊號電路 39
3.3 電路設計 40
3.4 預計規格與效能比較 43
3.5 晶片佈局 44
3.6 量測考量 45
3.7 電路模擬與晶片量測 46
3.7.1 電路模擬 46
3.7.2 晶片量測 47
第四章 結論及成果 49
參考文獻 50

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