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論文名稱 Title |
多功能數位轉換之參數化IP產生器 An IP Generator for Multifunctional Discrete Transforms using Parameterized Modules |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
62 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2004-07-05 |
繳交日期 Date of Submission |
2004-08-16 |
關鍵字 Keywords |
數位轉換、參數化 Parameterized Modules, Discrete Transforms |
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統計 Statistics |
本論文已被瀏覽 5619 次,被下載 18 次 The thesis/dissertation has been browsed 5619 times, has been downloaded 18 times. |
中文摘要 |
本論文中以N點數位轉換之快速演算法來實現移位式快速傅立葉轉換(SDFT),利用有效的矩陣分解來減少運算的複雜度,並將分解之矩陣分別映射到參數化的IP 模組上,再藉由串接這些IP模組,以實現各種類的數位轉換運算, 包括影像視訊壓縮常見的餘弦轉換(DCT)和音訊壓縮常見的 MDCT。由於各參數化的IP模組的規則性,可藉由改變參數,達到產生新的IP,再由這些新的IP去串接成各種類的數位轉換,這種硬體架構,具備有局部性、模組性、規律性、低成本、高產能等優點,並且由於快速傅立葉轉換本身的優點,在實現某些數位轉換的架構上,可以用較省的硬體去實現,或是可以擁有更佳的產能。 |
Abstract |
Fast algorithms for N-point shifted discrete Fourier transform (SDFT) are proposed by efficient matrix factorization.The resulted matrix decomposition is realized by a cascade of several basic computation blocks with each block implemented by a parameterized IP module.By combining these modules with different parameters, it is easy to implement a wide variety of digital transforms, such as DCT/IDCT in image/video coding, and modified DCT (MDCT) in audio coding. The transform processors realized using the parameterized IP modules have advantages of locality,modularity,regularity,low-cost,and high-throughput. Furthermore ,the computation accuracy can be easily controlled by selecting different numbers of IP modules with proper parameters in the processors. |
目次 Table of Contents |
CHAPTER 1 INTRODUCTION.................................................................................1 1.1 研究動機........................................................................................................1 1.2 準備工作........................................................................................................2 CHAPTER 2 OVERVIEW..........................................................................................4 CHAPTER 3 演算法與架構......................................................................................7 3.1 SHIFTED DFT .................................................................................................7 3.2 以SHIFTED DFT 計算DCT/IDCT..............................................................8 3.2.1 1D DCT/IDCT的 SDFT實現法..............................................................8 3.2.2用部分N點SDFT實現N點1D DCT/IDCT ................................................9 3.2.3用部分N點SDFT同時實現兩筆N點1D DCT.................................10 3.3以SHIFTED DFT 計算 MDCT ....................................................................12 3.4 SDFT的快速演算法.......................................................................................14 3.4.1 1D DCT/IDCT/MDCT的分解架構........................................................14 3.5基本元件的參數化設計 ...............................................................................16 3.5.1 BUTTERFLY 運算之IP設計................................................................17 3.5.2 CORIDC-BASED之旋轉 .......................................................................18 3.5.3 LIFTING-BASED之旋轉 ......................................................................20 3.6 1D DCT/IDCT/MDCT 之演算法..................................................................22 CHAPTER 4 硬體實作.............................................................................................26 4.1 參數化IP設計之簡介...................................................................................26 4.2 設計流程與驗證...........................................................................................27 4.3 參數化1D N-POINT DCT 和 TEST-PATTERN GENERATOR................29 4.4 參數化1D N-POINT IDCT 和 TEST-PATTERN GENERATOR...............35 4.5 參數化1D N-POINT MDCT 和 TEST-PATTERN GENERATOR.............39 4.6 誤差值的偵測與比較...................................................................................43 CHAPTER 5 分析與比較........................................................................................51 CHAPTER 6 應用....................................................................................................55 CHAPTER 7 總結和未來工作................................................................................60 參考文獻...................................................................................................................61 |
參考文獻 References |
[1]J. W.Cooley and J. W. Turkey “An algorithm for the machine computation of complex Fourier series”Math.Comput.vol1.19.no.90.pp.296-301,1965 [2]P. Duhamel, Y. Mahieux, and J. P. Petit, “A Fast Algorithm for the Implementation of Filter Banks Based on Time Domain Aliasing Cancellation”, Proc. ICASSP’91, pp. 2209-2212, May 1991. [3] S. Uramoto, Y. Inoue, A. Takabatake, J. Takeda, Y. Yamashita, H. Terane, and M. Yoshimoto, “A 100-MHz 2-D Discrete Cosine Transform Core Processor”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 4, pp. 492-498, Apr. 1992. [4] W.-R. Shiue,”A fast single chip implementation of a unified architecture for discrete trigonometric transforms “,National Sun Yat-sen University thesis of computer science ,July,1998. [5] S.-F. Hsiao and W.-R. Shiue, “A New Hardware-Efficient Algorithm and Architecture for Computation of 2-D DCTs on a Linear Array”, IEEE Trans. Circuits and Systems for Video Technologies, Vol. 11, No. 11, pp. 1149-1159, Nov. 2001. [6] J. H. Hsiao, L. G. Chen, T. D. Chiueh, and C. T. Chen, “High Throughput CORDIC-based Systolic Array Design for the Discrete Cosine Transform”, IEEE Trans. Circuits and Systems for Video Technologies, Vol. 5, No. 3, pp. 218-225, June 1995. [7] Y.-P. Lee, T.-H. Chen, L.-G. Chen, M.-J. Chen, and C.-W. Ku, “A Cost-Effective Architecture for 8x8 Two-Dimensional DCT/IDCT Using Direct Method”, IEEE Trans. Circuits and Systems for Video Technologies, Vol. 7, No. 3, pp. 459-467, June 1997. [8] S. Yu and E. E. Swartzlander Jr., “DCT Implementation with Distributed Arithmetic”, IEEE Trans. Computers, Vol. 50, No. 9, pp. 985-991, Sept. 2001. [9] N. Ahmed, T. Natarajan, and K. R. Rao, “Discrete Cosine Transform”, IEEE Trans. Computers, Vol. 23, pp. 90-93, 1974. [10] R. M. Haralick, “A Storage Efficient Way to Implement the Discrete Cosine Transform”, IEEE Trans. Computers, Vol. 25, pp. 764-765, July 1976. [11] T. D. Tran, “The BinDCT: Fast Multiplierless Approximation of the DCT”, IEEE Signal Processing Letters, Vol. 7, No. 6, pp. 141-144, June 2000. [12] S. B. Pan and R.-H. Park, “Unified Systolic Arrays for Computation of the DCT/DST/DHT”, IEEE Trans. Circuits and Systems for Video Technologies, Vol. 7, No. 2, pp. 413-419, Apr. 1997. [13] S.-F. Hsiao and Y.-H. Hu,”Unified Algorithms and Architectures for the Computation of Some Popular Transforms using Parameterized IP Modules”,Nov.2003. [14] K. R. Rao and P. Yip, “Discrete Cosine Transform: Algorithms, Advantages, Applications”, Academic, New York,1990 [15] S. Yu and E. E. Swartzlander, Jr., “A Scaled DCT Architecture With the CORDIC Algorithm”, IEEE Trans. Signal Processing, Vol. 50, No. 1, pp. 160-167, Jan. 2002. [16] J. Liang and T. D. Tran, “Fast Multiplierless Approximations of the DCT With the Lifting Scheme”, IEEE Trans. Signal Processing, Vol. 49, No. 12, pp. 3032-3044, Dec. 2001. [17] J.-I. Guo and C.-C. Li, “A Generalized Architecture for the One-Dimensional Discrete Cosine and Sine Transforms”, IEEE Trans. Circuits and Systems for Video Technologies, Vol. 11, No. 7, pp. 874-881, July 2001. |
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