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博碩士論文 etd-0817105-230520 詳細資訊
Title page for etd-0817105-230520
論文名稱
Title
用於系統層級架構模擬與評估之虛擬平台
A Virtual Platform for System-level Architecture Simulation and Evaluation
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
58
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2005-07-15
繳交日期
Date of Submission
2005-08-17
關鍵字
Keywords
軟硬體協同模擬、指令集模擬器
mp3, architecture exploration, Cosimulation, ISS, SystemC, master wrapper, simple bus, MAD, SWARM
統計
Statistics
本論文已被瀏覽 5659 次,被下載 2987
The thesis/dissertation has been browsed 5659 times, has been downloaded 2987 times.
中文摘要
著系統晶片複雜度日益複雜,系統設計者已經開始尋找可以處理複雜系統並且能夠儘速將產品導入市場的方法。最顯而易見的解決方法就是增加設計的抽象層次。然而,系統設計者最關心的是系統的架構(各元件的連結方式),軟硬體是否能夠達到需要的效能,以及元件之間的通訊協定。系統設計者必須在非常短的時間內決定這些架構。在這個時候,無論是速度以及所得到的資訊,交易層級模型是最能夠滿足這些需求的方法。
我們利用SystemC實做了一個交易層級模型虛擬原型平台,這裡包括了:各種包裝(wrapper)、指令集模擬器(ISS)、自訂的硬體 (ASIC)、以及一個有彈性的匯流排模擬架構。基於以上這些基礎元件,我們可以建立一個模擬的平台,以加速系統設計(system modeling)的流程。最後,我們將要利用這個系統模擬整個SoC的運作,以確保整個系統的功能正確,在模擬中收集的動態資料也可以用以分析系統中可能存在的瓶頸,藉此更進一步的改進系統架構。
Abstract
With complexities of Systems-on-Chip rising almost daily, the system designers have been searching for new methodology that can handle given complexities with increased productivity and decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However, the most important things that system designers care about are system architectures (components topology), HW/SW performance, and the communication protocols. System designer has to make decisions on these factors in a very short time. Furthermore, the transaction level model (TLM) can satisfy the requests on simulation speed and the information that system designer need.
We implement a TLM virtual prototype platform with SystemC composing with the variable wrappers. The basic modules: ISS interface, user-define modules and a flexible bus. Based on the infrastructures, a much faster modeling process of the system can be achieved in this thesis. Finally, the platform will run the whole-system-simulation to verify the functional model and collect the dynamic information on the buses and IPs to diagnose the bottle-neck of the system.
目次 Table of Contents
CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 CONTRIBUTION 3
1.3 ORGANIZATION 3
CHAPTER 2 SYSTEMC OVERVIEW 4
2.1 MODULES 6
2.2 INTERFACES, PORTS AND CHANNELS 6
2.1.2 Graphical Notations 8
2.3 PROCESSES AND EVENTS 9
2.4 HARDWARE-ORIENTED DATA-TYPE 10
CHAPTER 3 TRANSACTION LEVEL MODELING 11
3.1 ACCURACY MODEL OF TLM 11
3.2 TLM FOR ARCHITECTURE EXPLORATION DOMAIN 14
CHAPTER 4 RELATED WORK AND TOOLS 16
4.1 MASTER INTERFACE 16
4.1.1 Blocking Interface 16
4.2.1 Non-Blocking Interface 18
4.3.1 Direct Interface 19
4.2 PROCESSOR WRAPPERS 20
4.1.2 GDB Agent 20
4.2.2 Static Linked with SytemC Wrapper 22
4.3 THE TARGET CORE SIMULATORS 22
4.1.3 PIC simulators 23
4.2.3 SimpleScalar 24
4.3.3 The DLX Simulator 25
4.4.3 SoftWare ARM (SWARM) 25
4.4 SLAVE INTERFACE FOR CUSTOMIZED ASIC 27
4.1.4 General Slave Interface 27
CHAPTER 5 IMPLEMENTATION 29
5.1 THE MODIFIED SIMPLE BUS 29
5.2 CPU MASTER MODULE 31
5.1.2 SWARM Architecture 32
5.2.2 Master to Bus Interface 33
5.3.2 Memory Interface 34
5.3 MONITOR MASTER MODULE 37
5.4 THE LIBC USED FOR SWARM 37
5.5 SIMPLE DMA IMPLEMENTATION 39
5.6 CUSTOMIZED ASIC SLAVE 40
CHAPTER 6 EXPERIMENT 43
6.1 INTRODUCE TO THE MINIMAD 43
6.2 EXPERIMENTS 44
6.1.2 Pure Software 44
6.2.2 MP3 Accelerator with IMDCT Hardware 45
CHAPTER 7 CONCLUSION AND FUTURE WORK 46
7.1 CONCLUSION 46
7.2 FUTURE WORK 46
7.1.2 The more cycle accurate ISS should be studied 46
7.2.2 Multi-layered bus should be designed 47
CHAPTER 8 BIBLIOGRAPHY 48
參考文獻 References
[1] Gr
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