隨著全球化數位電視時代的來臨，如何掌握數位視訊廣播接收器的設計技術，顯得非常重要。在論文中針對數位視訊傳輸系統中關於通道解碼的協定，提出最佳化之積體電路架構。在此一協定中，通道編碼是採用連接碼之方式，由腓特比解碼、禮德-所羅門解碼器及內外解交錯等模組所構成。除了適當的算術運算元之外，這四個模組都需要很大的資料區塊儲存單元，因而本論文所提出的架構的主要特點乃是將所有大區塊的儲存單元都以記憶體的方式來實作，以降低所需電路面積及避免使用移位暫存器所造成極大的動態功率消耗。因此在腓特比解碼器的設計，利用演算法所具有之同位特性，並結合暫存器置換及回溯兩種路徑搜尋方式做為內部解碼，以達到高效率及低功率之腓特比解碼器架構。而關於禮德-所羅門解碼器之設計，乃基於序列柏林坎-瑪西修正後之演算法，並利用一新提出之最佳化的有限場域常數乘法器架構，以減少乘法器所須邏輯閘個數約達20%。在外部迴旋解碼器，提出一適當之位址產生器，並且將解交錯的資料路徑整合在兩塊記憶體上。而針對內部之符號交錯器，則以排列函數雙值同步的方式設計交錯位址器，所須記憶體比文獻記載減少一半。這四個模組已完成相當的整合測試，形成一個數位矽智產，提供各樣矽智產整合驗證所須的各種模組及自動驗證的機制。在場效可程式化邏輯陣列所發展的雛型設計已可達數位視訊廣播協定之要求。以台積電 0.35微米製程佈局的晶片，可達到面積25 mm2。

With the approach of the era of digital TV system around the world, how to grasp the design techniques of the receiver of the DVB-T has become a very important topic. The goal of this thesis is to pursue a highly optimized VLSI architecture compatible to the channel decoding standard of the DVB-T protocol. The channel decoding scheme adopted in DVB-T is based on the concatenated code; which is comprised of an inner Viterbi decoder, outer Reed-Solomon decoder and inner and outer de-interleaver modules. These modules all require a significant amount of data storage space, therefore the main feature of the proposed channel decoder architectures is to realize the data storage based on RAM instead of registers. This approach can lead to the reduction of silicon area and the dynamic power dissipation compared with the shift register based architecture. In order to achieve this, in the design of Viterbi module, the popular register-exchange and trace-back techniques used for the detection of the survivor path has been combined for the survivor memory management unit. As for the design of Reed-Solomon decoder, it is designed based on the modified inverse-free Berlekamp-Massey algorithm. A novel finite field constant multiplier architecture has been proposed which can reduce the required gate count of the multipliers by 20%. For outer convolutional deinterleaver, a specific address generator has been designed such that the data deinterleaver path can be merged and implemented as two memory blocks. For inner symbol deinterleaver, a lookahead technique has been applied to the design of address generator and deinterleaver memory has been reduced by a half compared with those in the literature. These four modules have been verified and integrated as robust channel decoder silicon IP. The related models used for IP integration and verification have also been provided. The prototyping on the FPGA has been tested to satisfy the requirement of the spec.

摘要 II
第一章 簡介 1
第二章 通道解碼器及各個模組的設計 4
2.1 Outer decoder 5
2.2 Outer deinterleaver 24
2.3 Inner deinterleaver 29
2.4 Inner decoder 33
2.5 System Architecture 40
2.6 常數有限場域乘法器之最佳化 41
第三章 通道解碼器的晶片與IP 45
3.1通道解碼器IP 45
3.2 實驗結果 47
第四章 結論 51
第五章 參考文獻 52

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