本論文所實作的靜態存取記憶體自動產生器，包含列解碼器、儲存細胞元、行解碼器，以及放大器及寫入控制器，其中在列解碼器我們所採用的pass-transistor的架構，此架構不僅在面積上有比NAND的列解碼器優秀，在實做上更是比NAND容易的多。而在行解碼器則是提供了兩種選擇，第一種是樹狀架構的行解碼器，第二種則是NOR預先行解碼器架構，提供兩種不同的方案給使用者，針對不同的需求做不同的選擇。雖然本篇論文只實作出SRAM的記憶體產生器，但已經將記憶體產生器做出一個完整的平台，也就是說在未來可以根據此架構的流程，實作出更多的記憶體產生器，如快去存取記憶體、移位暫存器、唯讀記憶體、暫存器組，以及內容可定址記憶體……等等。

The SRAM memory generator in this thesis is divided into four parts: row decoder, storage cell, column decoder, and sense amplifier & write controller. The row decoder is designed using pass-transistors logic with better area and regularity compared with conventional NAND based decoders. Two different column decoders, tree structure and NOR based predecoder, are provided in current version. Although only SRAM is implemented in this thesis, the memory generator platform is complete with all the necessary models required in the embedded design. In the future, other memories, such as cache, shift register, FIFO, stacks, ROM, register files, and content addressable memory, can be integrated in this memory generator platform.

Chinese Abstract
Abstract
List of Tables
List of Figures

Chapter 1 Introduction
1.1 Motivation
1.2 Current Research Status
1.3 Thesis Organization

Chapter 2 CMOS Memory Circuits
2.1 Storage Array
2.2 Row decoders
2.2.1 NAND Row Decoder
2.2.2 Pass-Transistor-Logic Row Decoder
2.3 Column Decoders
2.4 Writing Control and Bit Line Charge Circuit
2.5 Sense Amplifiers
2.6 Output Buffers
2.7 Summary

Chapter 3 Memory Generation: Cell-Based Design Flow and Artisan Memory Compiler
3.1 Cell-Based Flow for Memory Units
3.2 Artisan Memory Compiler

Chapter 4 Memory Hard IP Generator
4.1 Overview The Memory Generator30
4.2 Experimental Results

Chapter 5 Conclusions and Future Works
5.1 Conclusions
5.2 Future Works
Reference

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