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博碩士論文 etd-0819107-224652 詳細資訊
Title page for etd-0819107-224652
論文名稱
Title
管線化架構浮點CORDIC處理器之誤差分析、設計、實作及其應用
Implementation of Pipeline Floating-Point CORDIC Processor and its Error Analysis and Applications
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
105
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-30
繳交日期
Date of Submission
2007-08-19
關鍵字
Keywords
誤差分析、座標軸數位旋轉計算器、浮點數、管線化、幾何轉換
error analysis, 3D, CORDIC, floating-point, pipelined
統計
Statistics
本論文已被瀏覽 5678 次,被下載 3532
The thesis/dissertation has been browsed 5678 times, has been downloaded 3532 times.
中文摘要
在本論文中,將傳統的定點數(fixed-point)座標軸數位旋轉計算器(Coordinate Rotation Digital Computer, CORDIC)演算法之原理,推廣到浮點數(floating-point) CORDIC,以執行高精確度和高數值範圍之超越函數計算,如三角函數、指數、對數等。我們也根據不同演算法,實現了兩種高速 (high-throughput)管線式浮點數CORDIC架構硬體,其中一種架構中每個pipeline stage的移位運算是採用硬體移位器 (Barrel Shifter)設計,另一種架構中的移位運算是利用直接的拉線(hardwired)來實現。另外,本論文也根據不同的浮點數CORDIC演算法和架構,使用數學式分析其誤差,並與實際軟體程式之執行結果做比較。最後,本論文探討如何應用浮點數CORDIC硬體,來實現 3D 電腦圖形之旋轉相關運算。
Abstract
In this thesis, the traditional fixed-point CORDIC algorithm is extended to floating-point version in order to calculate transcendental functions (such as sine/cosine, logarithm, powering function, etc.) with high accuracy and large range. Based on different algorithm derivations, two different floating-point high-throughput pipelined CORDIC architectures are proposed. The first architecture adopts barrel shifters to implement the shift operations in each pipelined stage. The second architecture uses pure hardwired method for the shifting operations. Another key contribution of this thesis is to analyze the execution errors in the floating-point CORDIC architectures and make comparison with the execution resulting from pure software programs. Finally, the thesis applies the floating-point CORDIC to realizing the rotation-related operations required in 3D graphics applications.
目次 Table of Contents
第1章 導論 9
1.1 研究動機 9
1.2 本文架構 9
第2章 CORDIC原理與相關研究 11
2.1 CORDIC原理 11
2.1.1 演算法 11
2.1.2 架構 13
2.2 CORDIC相關研究 15
2.2.1 CORDIC演算法及架構之改進 15
2.2.2 CORDIC演算法之誤差分析 17
2.2.3 Floating-Point CORDIC 18
2.2.4 CORDIC應用 20
第3章 浮點數CORDIC誤差分析 22
3.1 簡易浮點數CORDIC 22
3.2 向量旋轉Vectoring 24
3.3 角度旋轉Rotation 26
3.4 模擬結果 29
3.5 結論 40
第4章 浮點數Redundant CORDIC及實作 42
4.1 浮點數CORDIC演算法 42
4.2 Pipeline浮點數Redundant CORDIC實作 45
4.2.1 前(後)置處理與前(後)置旋轉 45
4.2.2 內部Redundant CORDIC實作 47
4.2.2.1 移位運算使用硬體移位器(Barrel Shifter) 47
4.2.2.2 移位運算使用直接拉線(Hardwired Shifter) 50
4.3 驗證與實驗數據 55
4.3.1 浮點數Redundant CORDIC驗證 55
4.3.2 各項實驗數據 56
第5章 新架構浮點數CORDIC誤差分析 61
5.1 浮點數CORDIC使用Barrel Shifter 61
5.1.1 向量旋轉Vectoring 62
5.1.2 角度旋轉Rotation 65
5.1.2.1 小角度旋轉時Post Normalization的影響 66
5.1.2.2 大角度旋轉時Post Normalization的影響 69
5.2 浮點數CORDIC使用Hardwired Shifter 75
5.2.1 向量旋轉Vectoring 76
5.2.2 角度旋轉Rotation 79
5.3 模擬結果 82
5.3.1 FP. CORDIC使用Barrel Shifter模擬結果 82
5.3.2 FP. CORDIC使用Hardwired Shifter模擬結果 84
5.4 結論 88
第6章 Redundant CORDIC FPU之應用 90
6.1 Redundant CORDIC FPU應用在旋轉運算 90
6.1.1 旋轉運算簡介 90
6.1.2 設計與架構 95
6.2 效能比較 97
6.3 其他應用 98
第7章 結論 102
參考文獻 103
參考文獻 References
[1]. J. E. Volder, “The CORDIC trigonometric computer technique,” IRE Transactions. Electron. Computers, vol. EC-8, no. 3, pp. 330-334, Sept. 1959.
[2]. J. S. Walther, “A unified algorithm for elementary functions,” Proc. Spring Joint Compute. Conf. pp. 379-385, 1971.
[3]. Y. -H. Hu, “CORDIC-based VLSI architectures for digital signal processing,” IEEE Signal Processing Magazine, pp. 16-35, 1992.
[4]. J. R. Cavallaro and F. T. Luk, “Floating-point CORDIC for matrix computations,” Proc. IEEE Int. Conf. Computer Design: VLSI in Computers and Processors, pp. 40-42, 1988.
[5]. J. D. Bruguera, et al., “Design of a pipeline radix 4 CORDIC processor,” Journal of Parallel Computing, vol. 19, no. 7, pp. 729-744, 1993.
[6]. E. Antelo, et al., “High performance rotation architecture based on the radix-4 CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 8, pp. 855-870, Aug. 1997.
[7]. D. Timmermann, et al., “A CMOS floating-point vector-arithmetic unit,” IEEE Journal of Solid-State Circuits, vol. 29, no. 5, pp. 634-639, May 1994.
[8]. G. J. Hekstra and E. F. Deprettere, “Floating-point CORDIC:algorithm and architecture for a word-serial Implementation” Ph.D. dissertation, Dept. of Electrical Eng., Delft Univ., 1998.
[9]. J. Lee and T. Lang, “Constant-factor redundant CORDIC for angle calculation and rotation,” IEEE Transactions on Computers, vol. 41, no. 8, pp. 1,016-1,035, Aug. 1992.
[10]. H. Yoshimura, et al., “A 50-MHz CMOS geometrical mapping processor,” IEEE Transactions Circuits and Systems, vol. 36, no. 10, pp. 1360-1363, 1989.
[11]. T. Lang and E. Antelo, “High-throughput 3D rotations and normalizations,” Proc. 35th Asilomar Conf. Signals, Systems, and Computers, Nov. 2001.
[12]. T. Lang and E. Antelo, “High-throughput CORDIC-based geometry operations for 3D computer graphics,” IEEE Transactions on Computers, vol. 54, no. 3, pp.347-361, Mar. 2005.
[13]. T. -Y. Sung, et al., “A high-efficiency vector interpolator using redundant CORDIC arithmetic in power-aware 3D graphics rendering,” PDCAT CNF, pp. 44-49, Dec. 2006.
[14]. N. Takagi, et al., “Redundant CORDIC methods with a constant scale factor for sine and cosine computation,” IEEE Transactions on Computers, vol. 40, no. 9, pp. 989-995, Sept. 1991
[15]. M. D. Ercegovac and T. Lang, “Redundant and on-line CORDIC:application to matrix triangularisation and SVD,” IEEE Transactions on Computers, vol. 38, no. 6, pp. 725-740, June 1990.
[16]. H. Dawid and H. Meyr, “The differential CORDIC algorithm_Constant scale factor redundant implementation without correcting iterations,” IEEE Transactions on Computers, vol. 45, no. 3, pp. 307-318, Mar. 1996.
[17]. S. Wang and E. E. Swartzlander, “Merged CORDIC algorithm,” Proc. Int’l Symp. Circuits and System, pp. 1988-1991, 1995.
[18]. S. Wang, et al., “Hybrid CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1202-1207, Nov. 1997.
[19]. Y. -H. Hu, “The quantization effects of the CORDIC algorithm,” IEEE Transactions on Signal Processing, pp. 834-844, Apr. 1992.
[20]. X. Hu and S. C. Bass, “A neglected error source in the CORDIC algorithm,” Proc. 1993 IEEE ISCAS, vol. 1, pp.766-769, May 1993.
[21]. K. Kota and J. R. Cavallaro, “Numerical accuracy and hardware tradeoffs for CORDIC arithmetic for special-purpose processors,” IEEE Transactions on Computers, vol. 42, no. 7, pp.769-779, July 1993.
[22]. E. Antelo, et al., “Error analysis and reduction for angle calculation using the CORDIC algorithm,” IEEE Transactions on Computers, vol. 46, no. 11, pp. 1264-1271, Nov. 1997.
[23]. J. -C. Bajard, et al., “BKM:a new hardware algorithm for complex elementary functions,” IEEE Transactions on Computers, vol. 43, no. 8, pp.955-963, Aug. 1994.
[24]. D. S. Phatak, “Double step branching CORDIC:a new algorithm for fast sine and cosine generation,” IEEE Transactions on Computers, vol. 47, no. 5, pp.587-602, May 1998.
[25]. R. Farivar, et al., “A CORDIC-based processor extension for scalar and vector processing,” Proc. on 19th IEEE Int. Conf. Parallel and Distributed Processing Symposium, pp. 7, April 2005.
[26]. J. Ma, et al., “Pipelined CORDIC-based cascade orthogonal IIR digital filters,” IEEE Transactions on Circuits and Systems, vol. 47, no. 11, pp. 1238-1253, Nov. 2000.
[27]. J. Ma and K. K. Parhi, “Pipelined CORDIC-based state-space orthogonal recursive digital filters using matrix look-ahead,” IEEE Transactions on Signal Processing, vol. 52, no. 7, pp. 2102-2119, July 2004.
[28]. M. Parfieniuk and A. Petrovsky, “Structurally orthogonal finite precision implementation of the eight point DCT,” ICASSP, vol. 3, pp. 936-939, May 2006.
[29]. S. Y. Park and N. I. Cho, “Design of signed powers-of-two coefficient perfect reconstruction QMF Bank using CORDIC algorithms,” IEEE Transactions on Circuits and Systems, vol. 53, no. 6, pp. 1254-1265, June 2006.
[30]. Z. Liu, et al., “A floating-point CORDIC based SVD processor,” IEEE Application-Specific System, Architectures and Processors, pp. 194-203, June 2003.
[31]. K. Dickson, et al., “QRD and SVD processor design based on an approximate rotations algorithm,” SIPS Conference, pp. 42-47, 2004.
[32]. W. Ma, et al., “An FPGA-based singular value decomposition processor,” Electrical and Computer Engineering, Canadian Conference on, pp. 1047-1050, May 2006.
[33]. C. Y. Kang, et al., “An analysis of the CORDIC algorithm for direct digital frequency synthesis,” Proc. IEEE Int. Conf. on Application-Specific Systems: Architectures and Processors, pp. 111-119, July 2002.
[34]. W. Yang, et al., “A direct digital frequency synthesizer based on CORDIC algorithm implemented with FPGA,” ASIC, vol. 2, pp. 832-835, Oct. 2003.
[35]. D. Caro, et al., “Direct digital frequency synthesizers with polynomial hyperfolding technique,” IEEE Transactions on Circuits and Systems, vol. 51, no. 7, pp. 337-344, July 2004.
[36]. C. -C. Huang, “CORDIC-based sign-bit predictable SIN-COS generator and It’s FPGA Implementation,” Master thesis, Dept. of Computer Science and Engineering, National Sun Yat-sen University, July 2000.
[37]. S. -F. Hsiao, “Multidimensional CORDIC algorithms,” Ph.D. dissertation, Dept. of Electrical Eng., Yale Univ., Dec. 1993.
[38]. S. -F. Hsiao and J.-M. Delosme, “Householder CORDIC algorithm,” IEEE Transactions on Computers, vol. 44, no. 8, pp. 990-1001, Aug. 1995.
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