隨著微處理器系統的演進，單核心處理器系統所能增進的運算效率似乎已經達到了一個瓶頸，因此強調高效率的處理器逐漸傾向多核心的系統架構設計，再加上VLSI 製程技術的發展快速，Chip Multiprocessors 已不再遙不可及。
因此本論文提出單晶片多核心的超多純量（Hyper-scalar）系統架構，綜合超純量與多執行緒處理器架構，可多核心增進單一執行緒效能並支援多執行緒並行運算。系統可透過新增指令動態分配執行緒之核心群組數量，且利用虛擬共享暫存器的機制，解決各執行緒在多核心處理器內執行時指令間資料相依問題。
此虛擬共享暫存器機制可以讓各核心透過資料交換路徑至其他核心取得暫存器之內容值，依資料驅動的執行理念，待所有的運算元皆備妥後，指令才進行運算，因此相同的程式碼可以被派至不同數量之核心架構運算，而不需要額外的程式編譯動作，可以有效增進系統的運算效能且程式分派具有高度彈性。
而在效能評估方面，則利用SystemC 語言進行ESL 模型撰寫，提供硬體導向的模擬環境，並以MediaBench suite 為評估程式進行功能之驗証與效能之評估模擬。平均而言，超多純量系統架構在2 ~ 8 個核心架構中，可以獲得1.3 至2 倍的效能提升。

This paper proposed a scalable chip multiprocessor architecture, which is called Hyper-scalar combined with the concept of superscalar and multithreaded architecture; hence, this architecture can enhance single-threaded performance by using core group and also supports multithreaded applications. System programmer can dynamically allocate the core groups to accelerate a single thread by extended system instructions. In order to solve the data dependence between all issued instructions the virtual shared register file is proposed.
This mechanism allows the data in local register files to be accessed from other cores through the data switching path hardware and the instructions are executed only when the operands are available. The instructions within a single-threaded application can be dispatched to variable cores without re-compilation. This execution paradigm accelerates the single-threaded performance more flexibly.
In the case of simulation and experimental framework, the ESL Model written in SystemC, a modeling language based on C++ is to provide hardware-oriented simulation platform and the MediaBench suite is selected for the experiments. On average, the Hyper-scalar architecture can accelerate single-threaded performance by 30% to 110% using 2 ~ 8 cores.

摘要....................................................................................... i
ABSTRACT .........................................................................ii
目錄..................................................................................... iv
圖片列表............................................................................. vi
表格列表...........................................................................viii
第一章 簡介........................................................................ 1
1-1 研究動機.......................................................................1
1-2 研究目標.......................................................................2
1-3 論文架構.......................................................................3
第二章 相關研究................................................................ 4
2-1 單一核心架構介紹.......................................................4
2-2 目前多核心處理器架構...............................................5
2-2-1 多核心增進多執行緒效能之架構............................7
2-2-2 多核心增進單執行緒效能之架構............................7
2-3 資料驅動運行機制.....................................................14
2-4 超多純量系統架構之設計概念.................................16
第三章 超多純量系統架構設計...................................... 20
3-1 超多純量系統架構.....................................................20
3-2 多核心系統操作模式.................................................24
3-2-1 處理器群組方式.....................................................24
3-2-2 新增之系統指令.....................................................25
3-3 指令分析器設計.........................................................26
3-4 資訊處理單元設計.....................................................32
3-4-1 Data Stage.............................................................33
3-4-2 Commit Stage ......................................................38
3-5 虛擬共享暫存器設計.................................................39
3-5-1 VSRF Node 基本架構...........................................40
3-5-2 VSRF Switch 基本架構.........................................42
第四章 超多純量模型設計.............................................. 44
4-1 電子系統層級設計.....................................................44
4-2 單核心之ESL 模型設計............................................45
4-3 超多純量之ESL 模型與模擬環境............................50
第五章 驗証與模擬.......................................................... 53
5-1 模擬環境設定.............................................................53
5-1-1 效能評估方模擬方法.............................................53
5-1-2 效能評估程式.........................................................55
5-2 多核心架構與效能增進之關係.................................57
5-3 多核心架構與記憶體存取延遲時間之關係.............58
5-4 虛擬共享暫存器架構與效能增進之關係.................59
第六章 結論...................................................................... 62
參考文獻........................................................................... 64

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