可重新組態系統利用FPGA的partial reconfiguration的特性，提供數個重組區域，可以動態地載入不同的電路到某一重組區域，並且不影響到其它重組區域與系統其它部分的運作，大大提高了系統的彈性。若要實現動態重新組態，硬體必需提供兩項基本支援。首先，FPGA必需能支援局部組態功能。目前Xilinx的FPGA(如：Virtex-II、Virtex-IV)已支援此功能。再者，系統必需提供一個機制來動態的將電路載入到某一重組區域中。在這方面，Xilinx的ICAP(Internal Configuration Access Port) 也支援此功能。
然而，光靠上述兩項基本支援並無法完成一個自我重新組態的系統。本論文描述了建構一個自我重新組態的系統所需的設計流程與硬體支援。我們利用此流程實作了一個自我重新組態的系統。我們在FPGA上規劃了四個重組區域，並且實作動態載入機制，讓存在於快閃記憶體中的電路檔可以針對目前系統的需求動態地載入到所指定的重組區域中。此外，我們設計了一個靜態電路來達成軟體和重組電路間的資料傳遞。此靜態電路間透過FSL(Fast Simplex Link)與Microblaze處理器溝通，並透過一個統一的訊號介面與所有的重組電路溝通。根據實驗結果顯示，透過ICAP重新組態一個浮點數平方根的電路所花費的時間最多只需0.696秒，已達到了自我重組態系統實用的要求。

Reconfiguration systems use the partial reconfiguration characteristic of FPGA to dynamically load different bitstreams into different partial reconfiguration regions without affecting other active circuit areas. The hardware must provide two functions to support dynamic reconfiguration. First, the FPGA must support the partial reconfiguration function. Many Xilinx FPGAs such as Virtex-II and Virtex-IV have supported the function. Second, the FPGA must provide a way to load a partial bitstream into a specific region during the runtime. This can be achieved through the Xilinx Internal Configuration Access Port (ICAP).
However, the functions mentioned above are not sufficient for constructing a dynamic self-reconfiguration system. In this paper, we describe the design flow and the related hardware support for constructing such a system based on the aforementioned hardware functions. We have also implemented the system and the hardware support. In our system, partial bitstreams that were stored in the external flash memory can be loaded into one of the four reconfiguration regions on demand. Moreover, a static module in the system is used for communication between the processor (i.e., Microblaze) and the dynamically-loaded hardware. The static module communicates with Microblaze via FSL (Fast Simplex Link), and communicates with all the dynamically-loaded hardware modules via a uniform interface defined by us. According to the experimental results, configuring a floating-point square-root bitstream via ICAP requires only 0.696 second, which is acceptable in common cases.

誌謝 I
中文摘要 II
Abstract III
圖目錄 V
表目錄 VI
第一章 簡介 1
1.1 前言與動機 1
1.2 論文結構 4
第二章 相關研究 5
2.1 動態區域的規劃 5
2.2 靜態電路架構 6
2.3 自我重組態設計 6
第三章 設計與實作 7
3.1 自我重組態系統設計 7
3.1.1 Modular Design flow 和 EA PR flow 7
3.1.2 自我重新組態 10
3.1.3 Slice Bus Macro 與 TBUF Bus Macro 11
3.1.4 結合EA PR flow和Xilinx EDK (Embedded Development Kit) 15
3.2 自我重組態系統實作 17
3.2.1 EA PR flow檔案路徑結構 17
3.2.2 實作Top Level和Lower Level 18
3.2.3 測試EDK結合EA PR flow 19
3.2.4 靜態電路設計 21
3.2.5 內部reset機制 24
3.2.6 OPB HWICAP實作 25
3.3 系統架構 26
第四章 系統測試與分析 29
4.1 實驗發展平台及模擬軟體 29
4.2 系統靜態電路效能測試 30
4.2.1 靜態電路傳輸模擬 30
4.2.2 系統靜態電路效能 32
4.3 重組態電路效能測試 32
4.4 自我重組態效能測試 35
第五章 結論與未來工作 38
參考文獻 39

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