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博碩士論文 etd-0820108-032534 詳細資訊
Title page for etd-0820108-032534
論文名稱
Title
設計軟硬體協同設計平台-IRES
Design of the Software/Hardware Codesign Platform-IRES
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
93
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-07-23
繳交日期
Date of Submission
2008-08-20
關鍵字
Keywords
軟硬體協同設計、嵌入式系統、可重新組態運算
reconfigurable computing, embedded system
統計
Statistics
本論文已被瀏覽 5720 次,被下載 1869
The thesis/dissertation has been browsed 5720 times, has been downloaded 1869 times.
中文摘要
高效能可重新組態運算系統在處理高運算需求的應用程式上,已被證實具提昇系統效率的潛力;因此,現今的嵌入式系統朝著結合微處理器與可重新組態運算單元的趨勢發展;然而,這類型的系統架構,在軟硬體整合上卻面臨了溝通介面整合的問題。本論文針對嵌入式可重新組態運算系統,設計IRES軟硬體整合環境平台提升軟硬體間的整合度。在IRES中,透過I-link軟硬體檔案整合鏈結器來建立平台,產生單一可執行檔,內容包含:使用者設計的應用程式及硬體組態檔、系統提供的開機程式及作業系統與上述檔案產生出的資料前置區(PSP)。系統的初始由開機程式掃描單一可執行檔,藉由程式前置區建立程序控制區塊(TCB)、硬體控制區塊(HCB)以及硬體資訊區塊(NIB)資料結構。使用者透過這些資料結構取得硬體資訊,並利用系統提供的寫入、讀取等函式與硬體端溝通。透過硬體管理單元的建立,將可同時對多個加速硬體做溝通,並達到資料緩衝的效果。最後,我們成功利用實驗室所開發的平台(HSCP) 驗證了IRES軟硬體整合環境平台在軟硬體溝通機制上的完整性。
Abstract
High-performance reconfigurable computing has demonstrated its potential to accelerate demanding computational applications. Thus, the current trend is towards combining the microprocessor with the power of reconfigurable hardware in embedded system research area. However, integrating hardware and software that is the interface of communication is challenging. In this thesis, we present a methodology flow to improve the cohesion between hardware and software for reconfigurable embedded system design through IRES (I-link for Reconfigurable Embedded System), Hardware-Software integration platform. In IRES, we set up the platform and produce the Executor through I-link (Hardware-Software Integration Link). The Executor consists of tasks and hardware bitstreams which are provided by user design, bootloader and operation system which are provided by system, and PSPs (Program Segment Prefix) which are from the files given above. We initial the system through bootloader which will scan the PSPs of Executor to construct Task Control Block (TCB), Hardware Control Block (HCB) and Netlist IP Information Block (NIB) data structure. User can get the hardware information from those data structures, and communicate with hardware by using simple functions like “read()” and “write()”. Then, the system transmits the data to and from multi-hardware through Hardware Management Unit (HMU) which also has data buffering ability. Finally, we successfully accomplish IRES Hardware-Software integration platform in HSCP, which is developed in our laboratory, and verify the feasibility of communication between hardware and software.
目次 Table of Contents
摘要 iv
ABSTRACT v
圖目錄 ix
表目錄 xi
第一章 簡介 1
1-1 研究動機 1
1-2 研究目的 1
1-3 論文架構 2
第二章 相關研究 3
2-1 高效能可重新組態運算系統之特性 3
2-1.1 高效能可重新組態運算系統之研究 3
2-1.2 STARSoC架構於軟硬體溝通介面 6
2-1.3 MPSoC 自動產生軟硬體溝通介面平台 8
2-2 可重新組態運算系統之特性 11
2-2.1 可重新組態運算系統之相關研究 13
2-3 FPGA軟硬體協同設計背景 15
2-3.1 FPGA設定方式 15
2-3.2 JTAG下載方式 22
第三章 開機程式設計 24
3-1 IRES系統架構 24
3.2 IRES的建立 26
3.3 IRES的初始規劃 32
3-4 記憶體規劃 40
第四章 系統運作流程 44
4-1 軟硬體協同處理架構 44
4-2 硬體管理單元內部元件介紹 47
4-3 硬體管理單元暫存器介紹 52
4-4 軟體端與硬體溝通的撰寫方法 57
4-5 IRES的運作流程 63
第五章 平台實現與分析 68
5-1 驗證平台HSCP 介紹 68
5-1.1 平台的基本組件與連接 68
5-1.2 外部記憶元件與CPU的連接 70
5-1.3 FPGA與CPU的連接 71
5-1.4 平台運作模式 74
5-2 平台驗證與分析 75
第六章 結論 78
參考資料 79
參考文獻 References
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