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博碩士論文 etd-0820108-142507 詳細資訊
Title page for etd-0820108-142507
論文名稱
Title
應用並行MMX延伸指令集實現H.264演算法
The implementation of H.264 algorithm with parallel extended MMX instruction set
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
90
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-07-21
繳交日期
Date of Submission
2008-08-20
關鍵字
Keywords
多資料流、多媒體指令集、並行處理
multi-data-streaming, H.264, multimedia, MMX
統計
Statistics
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中文摘要
高畫質影像於可攜式嵌入式平台上實現的需求日益增加,H.264編解碼協定為當前高畫質平面視訊傳輸的重要協定,然而要於嵌入式系統上達到即時多媒體運算有其工作時脈上的限制,雖然許多加速多媒體運算的指令集被開發,多數仍難以在嵌入式系統低時脈的環境下實現即時運算。本論文希望藉由多資料流並行處理的SIMD架構「多媒體運算暫存器」實現H.264協定之演算法,以提升即時多媒體運算在嵌入式系統中的執行效率。多媒體運算暫存器是以位元切割運算的概念設計整合了暫存器細胞單元和多媒體運算機制,可藉由操作模式的切換改變資料處理的並行程度,並依據影像處理特性設計出與MMX指令集相容之多媒體指令集的處理單元。由於將運算單元及暫存單元整合,解決了原本資料分別以多媒體運算指令及一般指令處理時需經過額外的搬移動作這項缺點,並利用影像處理其資料於記憶體中位址有固定間距之特性,設計出跳躍式位址抓取定址模式並與多資料流並行運算合併使用。原本在處理H.264上耗費大量時間於眾多區塊中重複執行相同的指令,藉由多媒體運算暫存器多資料流並行處理能力可將眾多區塊一併處理,大量縮短執行時間,並利用操作模式的切換,有彈性的分配暫存器給各組位於多媒體運算暫存器中的運算器使用。原本在處理上較為費時的矩陣轉置、資料重新排序、SAD計算等動作,則藉由新增的行列互換指令、暫存器內區塊單獨搬移指令及針對市面既有的SAD計算指令的缺點加以改進所新增的指令,另輔以跨暫存器旋轉資料的方式令同一資料做最大限度的重複使用,使效能得到突破性的提升。於最後分析中本論文在處理H.264上效能為MMX的4倍以上,於SAD計算上甚至可達MMX的10倍,其效能更於現在最新的SSE4之上。
Abstract
The H.264 Protocol is an important method for the multimedia transmission and calculation, but it is difficult to work smoothly on the embedded systems because of the low clock in the working environment of the embedded system .Although many new multimedia instruction sets have been developed, the immediate multimedia calculation is still difficult to implement on the embedded system.
So this paper uses the “Multimedia Operation Register”, a SIMD architecture, to implement H.264 algorithm on the embedded system to improve the performance of handling multimedia calculation. Multimedia Operation Register, which performs the parallel execution of the multi-data-streaming, uses the bit slice concept to design operation pair combining bit storage cell and bit computation. According to the characteristic , which is the address having constant distance between more than two data being used saved in the Memory, this paper using the striping addressing mode , which can cooperate with the parallel execution of multi-data-streaming , to load the data having strode addresses from the Memory in one instructions. On the other hand, this paper designs a new instruction set based on the Intel MMX instruction set and the operation feature of multimedia calculation.
When a designer uses single-data-steaming to implement the H.264 Protocol by the multimedia instruction sets, he will use more interactions to do the same thing in every block. Now this paper can use fewer interactions to do the same thing because the Multimedia Operation Register can use the parallel execution of the multi-data-stream to calculate the data in many different blocks to implement H.264 Protocol at the same time. On the other hand, this paper can reallocate the number of the registers to the arithmetic unit which will be used smartly by changing the working mode. This paper also saves much execution time of some actions such as the transpose of the matrix, the data resorting and the SAD (Sum of Absolute Differences) calculation by using new instructions. In order to reduce the times of memory access, this paper uses the method which rotates the data between two registers to let the data been used as possible as it can. So the coding efficiency can be improved explosively by using all the methods which have been introduced.
The conclusion in this paper shows that the parallel execution of the multi-data-streaming will be a very important method to handle multimedia calculation. And this paper advances an innovative architecture to implement the parallel execution of the multi-data- streaming. According to the simulation in 5th chapter, the speedup of handling H.264 Protocol by Multimedia Operation Register is more than four times with MMX instruction set. In the SAD calculation, it even can have ten times advanced then MMX instruction set. At last the efficacy is even better than the latest multimedia instruction set -“SSE4”.
目次 Table of Contents
摘要 5
ABSTRACT 6
第一章 簡介 14
1-1研究動機 14
1-2研究目的 14
1-3論文架構 15
第二章 相關研究 16
2-1 H.264影像壓縮技術簡介 16
2-2 MMX簡介 26
2-3 SSE系列簡介 27
2-4 WMMX簡介 28
2-5多媒體運算暫存器簡介 28
2-6整理與討論 37
第三章 H.264於多媒體暫存器上的實現 40
3-1對多媒體運算暫存器的改良 40
3-2 H.264各流程評估 49
3-3 DCT於多媒體暫存器上的實現 53
3-4 Quantization於多媒體暫存器上的實現 56
3-5 Zigzag Scan於多媒體暫存器上的實現 58
3-6 Motion Estimation於多媒體暫存器上的實現 59
第四章 模擬平台的建立 62
4-1 開機動作 62
4-2 實踐平台的構成 63
4-3 溝通機制 66
第五章 模擬與分新 69
5-1 DCT效能評估 69
5-2 Quantization效能評估 73
5-3 Zigzag Scan效能評估 75
5-4 Motion Estimation效能評估 79
5-5 總體效能分析 84
5-6 模擬結論 86
第六章 結論 87
參考文獻 88
參考文獻 References
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[7] Stefano Tommesani, Intel SSE Instruction Set,http://www.tommesani.com/SSEPrimer.html.
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[15] ARM Inc.,“AMBA Specification (Rev 2.0),”available in http://www.arm.com/
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[17] Intel Corp,”Using MMX Instructions in a Fast iDCT Algorithem for MPEG Decoding,”March 1996.
[18] Intel Corp,”A Fast Precise Implementation of 8×8 Discrete Cosine Transform Using the Streaming SIMD Extensions and MMX Instructions,”Order Number: 742474-D01, April 1999.
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[23] Intel Corp,”Using MMX Instructions to Compute the AbsoluteDifference in Motion Estimation,”March 1996.
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