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博碩士論文 etd-0821100-150631 詳細資訊
Title page for etd-0821100-150631
論文名稱
Title
探討在單一系統晶片中內嵌式電路模擬器對多個內嵌微處理器之效能分析
Exploration of Multiple ICE’s for Embedded Microprocessor Cores in an SOC
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
62
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2000-07-28
繳交日期
Date of Submission
2000-08-21
關鍵字
Keywords
系統單一晶片、內嵌式電路模擬器
SOC, IP, ICE
統計
Statistics
本論文已被瀏覽 5719 次,被下載 1977
The thesis/dissertation has been browsed 5719 times, has been downloaded 1977 times.
中文摘要
電路除錯(debugging)及晶片測試(testing) 在晶片的生產中,佔了相當的時間。目前晶片設計朝向系統整合單一晶片(SOC)設計,電路越來越複雜,除錯及測試更是需要花時間。如何使除錯及測試的時間縮短,使得產品能快速上市(time-to-market),變得非常重要。
在單一系統晶片中,可能會含有多個微處理器,如ARM7TDMI及DSP等,如何對多個微處理器來進行測試及除錯,是我們此篇論文的課題。
我們設計一個能夠支援除錯及測試的機制,針對不同型態的微處理器,提出了三種不同的架構,使得系統整合者可以依據其所欲整合的微處理器型態來選擇適當的測試架構。這三種架構分別是:分散式架構、集中式架構及階層式架構。我們設計的測試機制為“內嵌式電路模擬器”(Embedded In-Circuit Emulator, E-ICE),以IEEE 1149.1的標準規格來設計。
此篇論文亦比較此三種架構的優缺點,及實驗數據。我們將以二個HT48100八位元微控器為例,以不同的時脈分別執行其程式,來驗證我們所提出的架構。

Abstract
SOC (System-On-Chip) designs are more and more popular, concurrently, more and more new challenges system integrators will meet. One out of these challenges is testing problem. Our research is focus on how to testing and debugging the microprocessor cores that embedded in an SOC. Not only test the microprocessor cores but also test the interconnecting wire among these embedded microprocessor cores. This thesis explores architectural alternatives in the integration of embedded in-circuit emulation (ICE) into an SOC chip with multiple micro-controller/processor cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed.
目次 Table of Contents
第一章 簡介 1
1.1. 研究動機 1
1.2. 研究方法 3
1.3. 論文大綱 3
第二章 微處理器測試之相關研究 5
2.1. 已提出之方法 5
2.2. 內嵌式電路模擬器 (EMBEDDED ICE) 7
第三章 背景資料 (BACKGROUND) 10
3.1. THE IEEE STD. 1149.1 BOUNDARY SCAN ARCHITECTURE 10
3.2. 中斷點偵測單元 (BREAKPOINT DETECTION UNIT) 16
第四章 POSSIBLE EMBEDDED ICE ARCHITECTURE 19
4.1. 分散式架構 (DISTRIBUTED ARCHITECTURE) 20
4.1.1. 特性及架構描述 20
4.1.2. 操作方法 24
4.1.3. 優點及缺點 29
4.2. 集中式架構 (CENTRALIZED ARCHITECTURE) 31
4.2.1. 特性及架構描述 31
4.2.2. 操作方法 35
4.2.3. 優點及缺點 35
4.3. 階層式架構 37
4.3.1. 特性及架構描述 37
4.3.2. 操作方法 40
4.3.3. 優點及缺點 41
第五章 不同架構之分析 42
5.1. 額外所需之邏輯閘(ADDITIONAL GATE COUNT) 43
5.2. 控制度(CONTROLLABILITY) 43
5.3. 測試週期(TESTING CYCLE) 46
5.4. 內嵌式電路模擬器和系統整合難易度(DIFFICULT DEGREE OF INTEGRATION ICE INTO SOC) 49
5.5. 整合後之重複使用性(INTEGRATION CORES REUSABILITY) 49
第六章 結論 51
第七章 未來工作 52
參考文獻 53

參考文獻 References
[1] IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society, New York, 1990.
[2] Ing-Jer Huang and Tai-An Lu, “ICEBERG: An Embedded In-circuit Emulator Synthesizer for Microcontrollers,” Design Automation Conference, 1999, Page(s): 580-585.
[3] Whetsel, L., “An IEEE 1149.1 Based Test Access Architecture for ICs with Embedded Cores,” Proc. International Test Conference, 1997, Page(s): 69-78.
[4] Bhattacharya, D., “Hierarchical test access architecture for embedded cores in an integrated circuit,” VLSI Test Symposium, 1998. Proceedings. 16th IEEE , 1998 , Page(s): 8 -14
[5] Prab Varma and Sandeep Bhatia, “A Structured Test Re-Use Methodology for Core-Based System Chips,” International Test Conference, 1998 IEEE, Page(s): 294-302.
[6] C. A. Papachristou, F. Martin and M. Nourani, “Microprocessor Based Testing for Core-Based System on Chip,” Proc. DAC 99, Page(s): 586-591.
[7] Praveen K. Jaini and Nur A. Touba, “Observing Test Response of Embedded Cores through Surrounding Logic,” Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on Volume: 1, 1999, Page(s): 119 -123 vol.1.
[8] Zorian, Y; Marinissen, E.J and Dey, S, “Testing Embedded-Core-Based System Chips,” Computer, Volume: 32 6 , June 1999 , Page(s): 52 –60.
[9] Bahram Pouya and Nur. A. Touba, “Modifying User-Defined Logic for Test Access to Embedded Cores,” International Test Conference, 1997 IEEE, Page(s): 60-68.
[10] ARM Ltd. Web Site,
http://www.arm.com/products/MICE/
[11] Winters, M., “Using IEEE 1149.1 for In-Circuit Emulation,” WESCON/94. Idea/Microelectronics. Conference, 1994, Page(s): 525 –528.
[12] Colin M. Maunder and Rodham E. Tulloss, “The Test Access Port and Boundary Scan Architecture,” IEEE Computer Society Press Tutorial, 1990.
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