在現今嵌入式處理器的設計中，除了注重在低功率消耗與降低設計的複雜度外，高效能也是必須的。由於製程技術的進步，藉著整合多個核心到單一顆處理器中，以成為增進效能的新趨勢。在本論文中以嵌入式處理器設計為考量，選擇了五階管線的ARM9處理器為核心，提出了一個超純量的雙核心架構。處理器設計了三種執行模式:單核心模式(single-core mode),超純量模式(superscalar mode)與多執行緒模式(multithreading mode)。利用新增的指令，讓雙核心處理器在程式執行時，能動態的從超純量執行切換成執行兩個並行的執行緒，建立了在程式內執行多執行緒的機制，是此雙核心處理器的一大特色，突破了傳統多處理器以只能執行程式間多執行緒的限制。而處理器在超純量模式下，有對作業環境不會有所影響與維持原來程式不用重新編譯的特性，讓此雙核心處理器也可直接用於已經開發完成的單核心處理器系統中，設計者不用因為處理器的替換而重新改寫已完成的程式。根據模擬的結果顯示，在處理器以超純量模式執行時，與單核心ARM9處理器比較，以在執行MPEG2的解碼程式最高有52%效能增進，其多媒體效能評估程式平均效能增進為41%，可以有效的提升ARM9處理器執行多媒體應用程式的效能。

In the design of the recently embedded processor, besides paying attention to low power consumption and reducing the complexity of the design, it is also necessary to be with high performance. Because of the advanced logic CMOS technology, incorporated multiple processor cores on a single chip becomes the new trend which improve performance. This thesis, being designed for the embedded processor, presents a superscalar dual core architecture for ARM9 ISA. The processor provides three operation modes: single-core mode, superscalar mode, and multithreading mode for designer. The processor can be switched dynamically in three mode with the new extended instructions, when it is executing the program. When the processor is executing in superscalar mode, the designer can use the processor without changing any setting of the original environment. According our simulation result, the superscalar dual core architecture can obtain 52% performance speedup when it execute the trace of MPEG2 decoder and obtain average 41% performance speedup comparing to the five-stage pipelined ARM9 architecture.

目錄
中文摘要 I
英文摘要 III
目錄 V
圖片列表 VII
表格列表 IX
第一章 簡介 1
1.1 研究動機 1
1.2 研究目標 2
1.3 論文架構 3
第二章 相關研究 4
2.1 單晶片多處理器 4
2.2 超純量處理器 7
2.2.1 靜態排程超純量處理器 8
2.2.2 動態排程超純量處理器 8
2.2.3 預先執行超純量處理器 10
第三章 支援超純量之ARM9指令集的雙核心架構設計 12
3.1 ARM9五階指令管線設計 12
3.2 支援超純量之ARM9指令集的雙核心架構 14
3.3 暫存器設計 15
3.3.1 單核心ARM9五階指令管線暫存器設計 15
3.3.2 雙核心架構戰存器設計 17
3.4 新增指令與範例程式 19
3.4.1 新增指令 19
3.4.2 指令格式 19
3.4.3 範例程式 20
3.5 雙核心處理器操作模式 25
3.5.1 單核心模式 25
3.5.2 超純量模式 25
3.5.3 多執行緒模式 28
3.6 中斷控制架構 30
3.6.1 單核心ARM9五階指令管線中斷控制 30
3.6.2 雙核心中斷控制 40
3.7 指令分配控制器 45
3.7.1 控制處理器模式的轉換 45
3.7.2 新增指令的預先解碼 47
3.7.3 指令的分派機制 47
第四章 模擬與分析 56
4.1 架構模擬 56
4.1.1 模擬環境 56
4.1.2 模擬器架構 57
4.1.3 效能評估程式 59
4.2 模擬結果與討論 60
第五章 結論 62
參考文獻 63

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