此篇論文提出以切換式電流電路(Switch-Current)的運用方式來完成取樣電路(Sample-and-Hold Circuit)之設計，論文中所探討的內容，主要是利用回饋(Feedback Circuit)電路來降低輸入阻抗，再利用對稱式差分複製(Coupled Differential Replicate)電路，以降低脈衝穿透誤差(Clock Feedthrough Error)。

在系統電路的實現上，我們採用了TSMC 0.35μm的互補式金屬氧化層半導體(Complementary Metal-Oxide-Semiconductor，CMOS)製程參數進行數據摸擬；採用差分式(Differential)AB類(Class-AB)的架構，在電源供應電壓1.5V、取樣頻率為40MHz、消耗功率為0.38mW的條件下，可得到目標訊號振幅與最大突波雜訊的相差值為55dB。

在電路設計方面，主要是針切換電流式取樣電路之架構及特性加以分析，並以Cadence Hspice模擬軟體驗證其功能。

In this thesis, a switched-current sample-and-hold circuit is proposed. We use feedback circuit to decrease the input impedance and to reduce the transmission error in SI cell. Furthermore, the entire memory cell is designed in a coupled differential replicate form to eliminate the clock feedthrough (CFT) error.

The sample-and-hold circuit is simulated using the parameters of TSMC 0.35μm CMOS process. The simulation results show that the spurious-free dynamic range (SFDR) is 55 dB, the sampling rate is 40MHz, the power consumption is 0.38 mW, and the power supply is 1.5V. Furthermore, the circuit is verified by cadence-hspice simulation.

Chapter1 Introduction..............................................................................................1
1.1 Background....................................................................................................1
1.2 Motivation......................................................................................................3
1.3 Thesis Organization .......................................................................................4
Chapter2 Sample-and-Hold Circuit........................................................................5
2.1 Switched-Current Circuit ...............................................................................5
2.2 Non-Ideal Behavior........................................................................................7
2.2.1 Mismatch Error ..................................................................................7
2.2.2 Transmission Error.............................................................................9
2.2.3 Clock Feedthrough Error .................................................................10
2.3 Compensation of Non-Ideal Behavior .........................................................15
2.4 Class-AB Switched-Current Techniques .....................................................19
2.4.1 Previous Class-AB Switched-Current Techniques ..........................19
A. Basic Class-AB Memory Cell.........................................................19
B. Low Voltage Class-AB SI Memory Cell.........................................21
C. Class-AB Two-Step Sampling SI Memory .....................................22
D. Low voltage, high speed, high resolution SI memory ....................23
Chapter3 The Proposed Class-AB Switched-Current Sample-and-Hold Scheme 24
3.1 Feedback Circuit ..........................................................................................24
3.2 Coupled Differential Circuit ........................................................................30
3.3 The Proposed Class-AB Switched-Current Sample-and-Hold Circut
.........................................................................................…………….33
IV
Chapter4 Simulation Result of the Proposed Sample-and-Hold Circuit...........34
4.1 Simulation Result.........................................................................................34
4.2 Comparing Different SI S/H Circuits Comparison......................................40
Chapter5 Conclusion ..............................................................................................41
References...................................................................................................................42

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