可重新組態運算系統需要強大的輔助設計環境支援，除了協助使用者建立軟、硬體之間的互動，對於可重新組態電路的佈局與繞行，亦是影響系統效能的重要關鍵。本論文實現用於FMRPU(多重內容之可重新組態運算單元)之佈局繞線工具。FMRPU雖為微顆粒之運算單元，但各個邏輯陣列之間的繞行結構為8位元對齊，所以一般以LUT為基礎的繞行模式，無法用在FMRPU的繞行上，因此我們提出以運算為基礎的設計模式，自外部輸入以運算為基礎之資料流程圖，經過壓縮後，利用模擬冶煉演算法，配合迷宮繞行或重心繞行演算法，將壓縮後的資料流程圖映射至FMRPU中。我們成功地將一些多媒體應用上的演算法，如FFT、DCT等，透過所實作出的工具，映射至FMRPU中。

Reconfigurable computing systems require supports from powerful computer aided design tools to help users developing the interactions between software programs and hardware circuits. The placement and routing support for reconfigurable processing units is also the key to the efficiency of the computing system. In this thesis, we implemented the placement and routing tool for the FMRPU (Fine-grain Multi-context Reconfigurable Processing Unit). The routing resource among the Logic Arrays supports only 8-bit aligned data width, so the routing of the FMRPU can’t completely imitate from the pattern used by LUT-based routing. Thus we proposed an operation-based design model which accepts a data flow graph that describes the operations of the circuit. After compressing the graph, the tool uses Simulated Annealing algorithm with either Maze Route or Center-of-Gravity Route to map the compressed graph into FMRPU. Through the placement and routing tool we implemented, we have successfully mapped several algorithms used in multi-media applications, such as FFT and DCT, into FMRPU.

摘要 1
ABSTRACT 2
目錄 3
圖目錄 5
表目錄 7
第一章 簡介 8
1-1 可重新組態運算之背景 8
1-2 可重新組態運算系統 10
1-3 可重新組態運算系統的編譯環境 11
1-4 研究目的 12
第二章 相關研究 13
2-1 FMRPU與商用FPGA之比較 13
2-2 LOCUSROUTE全域繞行演算法 14
2-3 CGE細部繞行演算法 16
2-4 VPR佈局與繞行工具 18
第三章 FMRPU的佈局與繞行 24
3-1 FMRPU的基本組件 24
3-2 LOGIC ARRAY的內部連結網絡 29
3-3 FMRPU的內部連結網絡 30
3-4 FMRPU佈局與繞行工具流程 34
3-5 預先定義的運算函式庫 37
3-6 資料流程圖描述語言 40
3-7 訂製運算 41
第四章 繞行演算法 44
4-1 LOGIC ARRAY的內部繞行 44
4-2 FMRPU模型建構 48
4-3 資料流程圖之壓縮 51
4-4 FMRPU之內部繞行演算法 53
4-5 FMRPU之佈局與繞行 57
第五章 效能評估 59
5-1 環境概述 59
5-2 映射之電路 60
5-3 效能與討論 66
第六章 結論 70
參考資料 71
附錄 73

[1]Jonathan Rose, “Parallel Global Routing for standard cells,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 9, Issue 10, Oct. 1990, pp. 1085-1095
[2]Stephen Brown, Jonathan Rose, “A Detailed Router for Field-Programmable Gate Arrays,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 11, Issue 5, May 1992, pp. 620-628
[3]Vaughn Betz, Jonathan Rose ”VPR: A New Packing, Placement and Routing Tool for FPGA Research,” Department of Electrical and Computer Engineering, University of Toronto
[4]Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh “MorphoSys: An Integrated Reconfigurable System for Data-Parallel Computation-Intensive Applications,” Computers, IEEE Transactions on Volume 49, Issue 5, May 2000, pp. 465-481
[5]Helena Krupnova, Gabriele Saucier “FPGA Technology Snapshot: Current Devices and Design Tools,” Institut National Polytechnique de Grenoble, CSI 46, Avenue Felix Viallet 38031 Grenoble Cedex, France
[6]Ellen M. Sentovich, Kanwar Jit Singh, Luciano Lavagno, Cho Moon, Rajeev Murgai, Alexander Saldanha, Hamid Savoj, Paul R. Stephan, Robert K. Brayton, Alberto Sangiovanni-Vincentelli, ”SIS: A System for Sequential Circuit Synthesis,” Electronics Research Laboratory, Memorandum No. UCB/ERL M92/41, Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA 94720
[7]Cong, J., Yuzheng Ding, “FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs,” Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 13, Issue 1, Jan. 1994, pp. 1-12
[8]S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, “Optimization by Simulated Annealing”, Science, May 13, 1983, pp. 671-680
[9]V. Betz and J. Rose, “Directional Bias and Non-Uniformity in FPGA Global Routing Architectures,” ICCAD, 1996, pp. 652-659
[9]”Berkley Logic Interchange Format(BLIF),” University of California, Berkeley, September 6, 1996
[10] Yen, I.-L. Dubash, R.M. Bastani, F.B, “Strategies for mapping Lee's maze routing algorithm onto parallel architectures,” Parallel Processing Symposium, 1993, Proceedings of Seventh International 13-16 April 1993, pp.672-679
[11]M. Huang, F. Romeo, and A. Sangiovanni-Vincentelli, “An Efficient General Cooling Schedule for Simulated Annealing,” ICCAD, 1986, pp. 381-384
[12]Mo, F. Tabbara, A. Brayton, R.K, “A force-directed maze router,” Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on 4-8 Nov. 2001, pp. 404-407
[13]Jason Cong, Yuzheng Ding, “Combinational logic synthesis for LUT based field programmable gate arrays,” ACM Transactions on Design Automation of Electronic Systems, Volume 1, Issue 2, April 1996, pp. 145-204
[14]Rulph Chassaing, “Digital Signal Processing Laboratory Experiments Using C and the TMS320C31 DSK”, Academic Press, 1998
[15]Ze-Nian Li, Mark S. Drew, “Fundamentals of Multimedia,” Pearson Education, 2004
[16]Xilinx Homepage, www.xilinx.com
[17]Altera Homepage, www.altera.com