現今的X86處理器都具有超純量的處理能力。超純量架構具有在一個週期內抓取、運算及結束多個指令能力，藉此來獲得更大的指令層級的平行度。但即使擁有超純量的處理能力，若處理器無法有效率地抓取多個指令而造成後端硬體空置，所能提升的效能也就有限。
程式指令的不連續是造成抓取效率低落的主因之一。這造成了前端在一個週期內所能看見的連續指令有限，即使提高了前端的指令抓取數也無法改善此情形。本論文中，我們提出了一分支目標緩衝器與指令流緩衝器架構，此架構具有預先取得分支資訊以及重組快取行的能力。我們藉由重組原快取行與下一個基本區塊所在的快取行，來讓前端能看到兩個基本區塊的連續指令，如此一來，前端不但能看到更多的有效指令，也能輕易地擷取跨越基本區塊的指令。模擬與實作的結果也顯示，在64位元組快取行與前端寬度為6個指令的系統下，可比原來的系統增加43.2%的抓取效率；並在4個快取行深度ABP緩衝器支援下，平均每週期能抓取3.6個有效指令。

Nowadays, X86 CPU all have superscalar computing ability. Superscalar architecture can fetch, execute and commit more than one instruction per cycle. And it helps a lot to explore more instruction level parallelism. If a superscalar processor fetches instructions inefficiently, its performance speedup ratio will be limit.
Program flow is not continuous. It is one of main reasons that Front-End can’t fetch efficiently. And it is useless to get more speedup by enlarging fetch capacity of Front-End or other units. In this thesis, we present a new structure of branch target buffer and instruction stream buffer. They have abilities to predict advance branch information and reassemble cache lines. Front-End could fetch more valid instructions in a cycle by reassembling original line and line which contains instructions of the next basic block. The simulation and implement results show that we can get 43.2% speedup in fetch efficiency with 64 bytes cache line size and 6 fetch capacities. And 3.6 valid instructions per cycle with ABP buffer which buffers 4 cache line.

中文摘要 2
英文摘要 3
目錄 4
圖目錄 6
表目錄 8
第一章 簡介 9
1-1 研究動機 10
1-2 研究目標 13
1-3 論文架構 14
第二章 相關研究 15
2-1 預先抓取指令 15
2-2 分支預測 18
2-3 ABP緩衝器與指令預先解碼 21
2-3-1 ABP緩衝器 22
2-3-2 指令預先解碼 23
第三章 分支目標緩衝器的設計 27
3-1 分支目標緩衝器的讀取機制 28
3-2 分支目標緩衝器的內部結構 29
3-3 結合分支目標緩衝器與預測單元 34
第四章 指令流緩衝器的設計 36
4-1 概論 36
4-2 抓取循序器 38
4-3 重組單元與指令擷取單元 41
4-3-1 快取行重組單元 41
4-3-2 指令群重組單元 43
4-3-3 程式計數器產生器 45
4-4 高速設計下的硬體架構 46
第五章 模擬與分析 49
5-1 效能評估程式 49
5-2 分支目標緩衝器的模擬與分析 51
5-3 指令流緩衝器的模擬與分析 55
5-3 硬體的合成與分析 62
第六章 結論 65
參考文獻 67

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