隨著可攜式計算裝置與無線通訊系統的普遍使用，降低能量消耗便成為VLSI設計的主要目標。在許多數位信號處理器和多媒體系統中，乘法器是一個主要的基本元件並且深深的影響整個系統的效能與能量的消耗。因此，乘法器的設計顯得格外重要而必須謹慎考量。此外這些系統中可能出現不同的應用在同一套硬體上運作的情形，因而產生多種不同的輸入資料寬度。根據這項輸入資料的特徵，本篇論文提出了一個不需要額外可程式化裝置的可重置乘法器架構。這個乘法器採用Booth的演算法以減少將近一半的部份乘積並且實現有號數的乘法，為了讓這個可重置乘法器達到節省能量消耗的目標，我們使用攔截時脈訊號的技術來關閉不需要計算的部份電路。此外，此篇論文提出的節能乘法器能夠運算不同的資料位元數，進一步降低能源浪費並提高效能。
本篇論文提出兩個版本的乘法器。第一個版本是可重置性管線化Booth乘法器，這個乘法器可以執行一個n位元乘以n位元的乘法或者同時執行兩個n/2位元乘以n/2位元的乘法。當乘法器在運算n位元乘法時，可以根據運算資料來關掉一些區塊，使得能源消耗更符合效益，第二個版本進一步的採用了截斷的功能以提供不同方法讓乘法運算更符合能量消耗的效益。實驗的結果顯示我們所提出的乘法器在處理乘法運算時不只提高能量消耗的效益並且減少了能量的浪費。由於提供較多的功能性，我們提出的乘法器也需要更多的額外面積。

With the portable computing devices and wireless communication systems are popularly used, the power consumption became one of the major targets of VLSI design. However, multiplier is always a fundamental component and influences the power consumption and performance much in many DSP and multimedia applications. Therefore, multiplier is the crucial design and need to be concerned at first. In these systems, the data width of input data is various because the different applications are operated in the same system. According to this characteristic of input data, this paper presents architecture of reconfigurable multiplier without the necessity to completely reconfigure the internal layout of a programmable device. The multiplier employs the Booth algorithm which reduces the partial products to half to implement the sign multiplication. In order to reduce power consumption, the proposed multiplier introduces the clock gating technique to disable the circuit which does not need to be computed. Moreover, the energy-efficient multiplier presented in this thesis can perform multiplication with different data widths to further decrease power dissipation and enhance performance.
In this work, we proposed two versions of multipliers. The first version is reconfigurable pipelined Booth multiplier, which can perform one n by n multiplication or two n/2 by n/2 multiplications concurrently. When the multiplier performs n-bit multiplication, it can reduce power consumption by disabling the unnecessary blocks according to the input data. The second version further deploys the truncated functionality to provide different way to make multiplication more energy-efficient. Experiment shows that the proposed multipliers can perform multiplication with less energy and lower power dissipation. It is certain that the more functions the design provides, the more area it will cost.

CHPATER 1 Introduction 1
1.1 Motivation 1
1.2 Previous Survey 3
1.3 Thesis Organization 5
CHPATER 2 Related Work 6
2.1 Radix-4 Booth Multiplier 6
2.1.1 Recoding Unit 7
2.1.2 Partial Product Generator 9
2.1.3 Summated Adder 10
2.1.4 Final Adder 13
2.2 Dynamic Range Determination Unit 13
2.3 Left to Right Leapfrog Multiplier 15
2.4 A Low-power Booth Multiplier Using Novel Data Partition Method 20
2.5 A Self-Compensation Fixed-Width Booth Multiplier and Its 128-point FFT Applications 24
2.6 Low Power Technique 27
CHPATER 3 Proposed Reconfigurable Pipelined Booth Multiplier 32
3.1 Introduction 32
3.2 Formulation 34
3.3 Condition of Mode 37
3.4 Architecture 43
3.5 Input Detection Unit (IDU) 46
3.5.1 Dynamic Range Determination Unit (DRD) 47
3.5.2 Block Detection Unit (BDU) 52
3.5.3 Mode Generator 56
3.6 Equation Compensated Value Unit (EC) 57
3.7 Compression Tree 59
3.8 Signed Compensated Value Unit (SC) 61
3.9 Summation Tree 67
CHPATER 4 Proposed Reconfigurable Truncated Pipelined Booth Multiplier 69
4.1 Introduction 69
4.2 Condition of Mode 70
4.3 Architecture 71
4.4 Block Detection Unit (BDU) 72
4.5 Partial Product Generator (PPG) 74
CHPATER 5 Experiment and Analysis 79
5.1 Implementation 79
5.2 Generator 79
5.3 Experimental Result and Analysis 80
5.4 Floorplan 87
CHPATER 6 Conclusion and Future Work 89
6.1 Conclusion 89
6.2 Future Work 89

[ 1 ] Behrooz Parhami, Computer Arithmetic Algorithms and Hardware Designs, Oxford university press, 2000.
[ 2 ] Jongsu Park, San Kim and Yong-Surk Lee, “A Low-Power Booth Multiplier Using Novel Data Partition Method,” IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp. 54-57, August 2004.
[ 3 ] Jiun-Ping Wang, Shiann-Rong Kuang and Yuan-Chih Chuang, “Design of Reconfigurable Low-Power Pipelined Array Multiplier,” International Conference on Communications, Circuits and Systems, Volume 4, pp. 2277-2281, June 2006.
[ 4 ] Oscal T.-C. Chen, Sandy Wang, and Yi-Wen Wu, “Minimization of Switching Activities of Partial Products for Designing Low-Power Multipliers,” IEEE Transactions on Very Scale Integration (VLSI) Systems, Vol. 11, No. 3, pp. 418-433, June 2003.
[ 5 ] Hanho Lee, “Power-Aware Scalable Pipelined Booth Multiplier,” IEICE Transaction Fundamentals, Vol. E88-A, No. 11, pp. 3230-3234, November 2005.
[ 6 ] Shaolei Quan, Qiang Qiang and Chin-Long Wey, “A Novel Reconfigurable Architecture of Low-Power Unsigned Multiplier for Digital Signal Processing,” IEEE International Symposium on Circuits and Systems, vol. 4, pp. 3327-3330, 2005.
[ 7 ] Pedram Mokrian, Majid Ahmadi, Graham Jullien and W.C. Miller, “A Reconfigurable Digital Multiplier Architecture,” Canadian Conference on Electrical and Computer Engineering, Vol. 1, pp. 125-128, May 2003.
[ 8 ] Albert N. Danysh and Earl. E. Swartzlander Jr., “A Recursive Fast Multiplier,” Conference Record of the Thirty-Second Asilomar Conference on Signals, Systems & Computers, Vol. 1, pp. 197-201, November 1998.
[ 9 ] Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou, “Sub-Word and Reduced-Width Booth Multipliers For DSP Applications,” IEEE International Symposium on Circuits and System, Vol. 3, pp. 575-578, May 2002.
[ 10 ] Magnus Själander, Henrik Eriksson and Per Larsson-Edefors, “An Efficient Twin-Precision Multiplier,” IEEE International Conference on Computer Design : VLSI in Computers and Processors, pp. 30-33, October 2004.
[ 11 ] Whitney J. Townsend, Eael E. Swartzlander, Jr. and Jacob A. Abraham, “A comparison of Dadda and Wallace multiplier delays,” Proceedings of the SPIE Advanced Signal Processing Algorithms, Architectures, and implementations XIII, Vol. 5205, pp. 552-560, 2003.
[ 12 ] E.E. Swartzlander Jr., “Merged arithmetic,” Vol. 29, pp. 946-950,1980.
[ 13 ] K.A.C. Bickerstaff, M. Schulte, and E. E. Swartzlander Jr., “Reduced area multipliers,” Intl. Conf. on Application-Specific Array Processors, pp. 478-489, 1993.
[ 14 ] Nan-Ying Shen, Oscal T.-C. Chen, “Low-Power Multipliers by Minimizing Switching Activities of Partial Products,” IEEE International Symposium on Circuits and Systems, Vol. 4, IV-93 - IV-96, 2002.
[ 15 ] M.D. Ercegovac and T. Lang, “On-the-fly conversion of redundant into conventional representations,” IEEE Trans. Comput., Vol. C-36(7):895-897, July 1987.
[ 16 ] M.D. Ercegovac and T. Lang, “Fast multiplication without carry-propagate addition,” IEEE Trans. Comput. C-39(11):1385-1390, November 1990.
[ 17 ] Zhijun Huang and M. D. Ercegovac, “High-Performance Left-to-Right Array Multiplier Design,” IEEE Symposium on Computer Arithmetic, pp. 4-11, 2003.
[ 18 ] Zhijun Huang and M. D. Ercegovac, “High-Performance Low-Power Left-to-Right Array Multiplier Design,” IEEE Transactions on Computers, Vol.54, No.3, pp. 272-283, March 2005.
[ 19 ] Zhijun Huang, High-Level Optimization Techniques for Low-Power Multiplier Design, A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Computer Science, 2003.
[ 20 ] Ravi K. Kolagortla, Hosahalli R. Srinivas and Geoffrey F. Burns, “VLSI Implementation of a 200-MHZ 16×16 Left-to-Right Carry-Free Multiplier in 0.35 μm CMOS Technology for next-generation DSPs,” Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 469-472, May 1997.
[ 21 ] Shivaling S. Mahant-Shettic and Poras T. Balsara, “High Performance Low Power Array Multiplier Using Temporal Tiling,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 7, No. 1, pp. 121-124, March 1999.
[ 22 ] Hong-An Huang, Yen-Chin Liao, and Hsie-Chia Chang, “A Self-Compensation Fixed-Width Booth Multiplier and Its 128-point FFT Applications,” IEEE International Symposium on Circuits and System, 2006.
[23] Massoud Pedram and Jan M. Rabaey, Power Aware Design Methodologies. Kluwer Academic Publishers, 2002.
[ 24 ] TSMC 0.18 μm Process 1.8-Volt SAGE-X Standard Cell Library Databook. Artisan Components, Inc., Oct. 2003.