本論文之主要目的在於設計與實現符合DVB-T數位視訊廣播系統接收器之相關演算法運算所需之高效能數位訊號處理器，提供即時之資料處理以產生足夠的訊號流的輸出。其中需即時完成8192點之FFT運算是本論文最重要的關鍵。
在不使設計的處理器時脈太高的前提之下，為了達到即時完成FFT的需求，提高指令並行度是唯一的方法。因此本論文針對FFT演算法設計了一個VLIW架構之運算核心，稱作DVB-T DSP，以提供足夠之執行單元支持指令並行，並利用Software Pipelining的方式將迴圈重新排程以達到在處理FFT之Butterfly運算時具有最佳之指令並行度。另外，為了能提供順暢的資料流，本論文針對FFT向量運算之特性，改良數位訊號處理器的Modulo Addressing之運算機制，稱作Extended Modulo Addressing，使得原本離散的向量能被視為一新的連續向量，避免了因資料不連續所造成的管線延遲。
在VLIW架構處理器中，指令碼膨脹是一個很大的問題，為了解決這個問題，本論文提出一種指令壓縮的機制，能在不影響原有的處理器執行效率下，提高兩倍左右的程式密度。
根據模擬分析的結果，此架構在執行FFT運算僅需133Mhz的速度即可達到DVB-T之要求。而在執行其他數位訊號處理之演算法上，也可以達到極好的效能。

The main goal of this thesis is to design and implement the high performance processor core for completing those digital signal processing algorithms applied at the DVB-T systems. The DSP must support the signal flow in time. Completing the FFT algorithm at 8192 input signal points instantaneously is the most important key.
In order to achieve the time demand of FFT and the DSP frequency must be as lower as possible, the way is to increase the degree of instruction level parallelism (ILP). The thesis designs a VLIW architecture processing core called DVB-T DSP to support instruction parallelism with enough execution units. The thesis also uses the software pipelining to schedule the loop to achieve the highest ILP when used to execute FFT butterfly operations. Furthermore, in order to provide the smooth data stream for pipeline, the thesis designs a mechanism to improve the modulo addressing, called extended modulo addressing, will collect the discrete vectors into one continuous vector.
This is a big problem that the program size is bigger than other processor architecture at the VLIW processor architecture. In order to solve the problem, this thesis proposes an instruction compression mechanism, which can increase double program density and does not affect the processor execution efficiency.
The simulation result shows that DVB-T DSP can achieve the time demand of FFT at 133Mhz. DVB-T DSP also has good performance for other digital signal processing algorithms.

摘要 I
英文摘要 III
目錄 V
圖片列表 VII
表格列表 IX
第一章 導論 1
1.1 數位訊號處理器架構與現在之發展趨勢 1
1.2 研究動機與研究目的 5
1.3 論文架構 6
第二章 相關研究 7
2.1 VLIW 7
2.2 編譯器與指令層級之並行 9
2.3 向量化處理器 11
2.4 具向量化運算之數位訊號處理器 13
第三章 向量化運算 16
3.1 FFT演算法 16
3.2 向量化指令排程 23
3.3 增進向量化指令效率與排程結果分析 25
第四章 指令壓縮 27
4.1 指令壓縮機制 27
4.2 解壓縮硬體結構 31
4.3 壓縮率 33
第五章 DVB-T DSP架構 34
5.1 架構概述 34
5.2 暫存器 37
5.3 記憶體定址模式 41
5.3.1 Indirect Addressing 41
5.3.2 Modulo Addressing 42
5.3.3 Extended Modulo Addressing 43
5.3.4 Bit Reversal Addresssing 44
5.4 Zero Overhead Looping 46
5.5 指令集 48
5.5.1 ALU Instruction 48
5.5.2 Multiplier Instruction 50
5.5.3 Load Instruction 52
5.5.4 Store Instruction 54
5.5.5 Branch Instruction 56
5.5.6 Zero Overhead Looping Instruction 57
第六章 驗證與分析 58
6.1 驗證與模擬環境 59
6.2 硬體合成與驗證結果 60
6.3 分析結果 62
第七章 結論 70
附錄 72
參考文獻 78

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