Responsive image
博碩士論文 etd-0824100-200034 詳細資訊
Title page for etd-0824100-200034
論文名稱
Title
針對ARM7TDMI微處理器進行成本和效能之微架構最佳化設計
Cost-effective Microarchitecture Optimization for ARM7TDMI Microprocessor
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
72
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2000-07-28
繳交日期
Date of Submission
2000-08-24
關鍵字
Keywords
最佳化、效能、微處理器、驗證
ARM7TDMI, OPTIMIZATION, PERFORMANCE, MICROPROCESSOR, COST-EFFECTIVE, VERIFICATION
統計
Statistics
本論文已被瀏覽 5670 次,被下載 2901
The thesis/dissertation has been browsed 5670 times, has been downloaded 2901 times.
中文摘要
在本篇論文中,我們描述如何去將ARM7TDMI這顆微處理器作微架構的最佳化設計。ARM7TDMI是ARM Ldt. 所發展的一顆32位元的微處理器。它使用在嵌入式的運用上,像是行動電話、呼叫器和個人數位處理(PDA)。ARM7已經擁有許多成功的經驗並結合低功率、低成本和高效能等特性。然而,當產品的運用變得愈來愈複雜而且加入更多功能,微處理器就被要求提供更高的效能。我們使用合成軟體來合成我們的RTL設計,並且分析timing來找出最長的延遲路徑。我們利用簡單的硬體調整,不需要增加太多複雜的電路,來達到效能最佳化的目的。我們將描述如何作最佳化設計來增進效能。
Abstract
In this paper, we present how to optimize our ARM7TDMI instruction set compatible microprocessor. The ARM7TDMI is a 32-bit microprocessor developed by ARM Ldt. It used in embedded application such as mobile phones, pager and PDAs. The ARM7 family owes its success to the combination of low power, low cost and high performance. However, as applications become more complex and integrate more and more functionality, the processor is required to provide more and more performance. We tune the hardware simply, no use complex hardware, to complete performance optimization. We use synthesis tool to synthesize our RTL design and analyze timing to fund the critical path of our microprocessor. We will describe how to optimize the critical path to increase performance.
目次 Table of Contents
1. 簡介 1
1.1 研究動機 1
1.2 研究方法 1
1.3 論文大綱 2
2. 相關研究 3
2.1 ARM7TDMI 3
2.2 ARM9 4
3. NSYSU之ARM7TM微架構設計 7
3.1 管線式(PIPELINE)架構 7
3.2 FETCH STAGE 8
3.3 DECODE STAGE 9
3.4 EXECUTE STAGE 11
3.5 乘加器之設計 13
3.6 PIPELINE的控制 16
3.7 中斷(EXCEPTIONS) 19
4. 最長延遲路徑之最佳化 22
4.1 最長延遲路徑(CRITICAL PATH) 22
4.2 乘加器之最佳化 24
4.2.1 使用單一時脈觸發 24
4.2.2 使用Carry Save Adder 25
4.2.3 改進部分乘積之計算 26
4.2.4 控制部分之最佳化 27
4.3 EXECUTE STAGE之最佳化 28
4.3.1 使用單一時脈觸發 28
4.3.2 Register File之改良 29
4.3.3 Condition延後決定 29
4.4 提前提取REGISTER FILE運算子 30
4.4.1 控制訊號提前至decode stage解碼 31
4.4.2 Data Hazard 31
4.4.3 pipeline的控制 33
4.4.4 改善Condition以符合ARM7TDMI之CPI值 37
4.5 結果 38
5. FPGA之實作 42
6. 結論 45
7. 未來展望 46
8. 附錄
參考文獻 References
[1] http://www.arm.com

[2] Simon Segar, “The ARM9 Family – High Performance Microprocessors for Embedded Applications” IEEE International Conference on Computer Design 1999 (ICCD’99).

[3] Steve Furber “ARM System Architecture” Addison Wesley Longman Inc, 1996.

[4] Michael Keating and Pierre Bricaud “Reuse Methodology Manual for System-on-a-Chip Designs”, 2nd Edition, KLUWER ACADEMIC PUBLISHERS.

[5] “DesignWare Components Databook, Vol 1, Foundation Librarys”, Version 1997.08, Synopsys Inc.

[6] David A. Patterson and John L. Hennessy, “Computer Origanization & Design – The Hardware/Software Interface”, 2nd Edition, Margan Kaufmann Publishers, Inc.

[7] John L. Hennessy and David A. Patterson, “Computer Architecture A Quantitative Approach” 2nd Edition, Margan Kaufmann Publishers, Inc.

[8] Behrooz Parhami, “Computer Arithmetic - Algorithms and Hardware Designs”, Oxford University Press, Inc.

[9] Mike Clark and Lizy Kurian John, “Performance Evaluation of Cinfigurable Hardware Features on the AMD-K5”, IEEE International Conference on Computer Design 1999 (ICCD’99).

[10] James K. Huggins, David van Campenhout, “Specification and Verification of Pipelining in the ARM2 RISC Microprocessor”, ACM Transactions on Design Automation of Electronic Systems, October 1998.

[11] Jeremy Levitt and Knule Olukotun, “A Scalable Formal Verification Methodology for Pipelined Microprocessors”, 33rd Design Automation Conference,1996.

[12] Jian Shen and Dave Baker, “Functional Verification of the Equator MAP1000 Microprocessor”, Design Automation Conference,1999.

[13] Warren A. Hunt, Jr. and Jun Sawada, “Verifying The FM9801 Microarchitecture”, IEEE Micro, MAY-JUNE 1999.

[14] Ray Turner, “System Level Verification – a Comparison of Approaches”, Rapid Systems Prototyping, 1999. IEEE International Workshop.

[15] Michael Gschwind and Dietmar Maurer “An Extendible MIPS-I processor kernel in VHDL for hardware/software co-design”, EURO-DAC ’96.

[16] Mayan Moudgill, John-David Wellman and Jaime H. mereno, “Environment for PowerPC Microarchitecture Exploration”, IEEE Micro, May-June 1999.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外完全公開 unrestricted
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available


紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code