在本論文中，具有比傳統全覆通道式閘極GAA特性還要良好的高效能假閘極全環繞矽覆絕緣PGAA（Pseudo-Gate-All-Around）SOI MOSFET元件已經成功被製作出來了。在本論文所作製作的3D結構新高效能假閘極全環繞矽覆絕緣PGAA SOI MOSFET元件結構具有下列四項特點：

（1）、 使用新高效能假閘極全環繞矽覆絕緣PGAA元件代替傳統單一閘極元件結構：在新元件的結構中，除了矽晶膜層上方的多晶矽閘極之外，我們更在矽晶膜層的下方向和前後兩面的方向，製作出了近似四面閘極，可以達到提高元件的閘極控制能力和電流驅動力。

（2）、 模擬多晶矽和單晶矽的新高效能假閘極全環繞矽覆絕緣元件與傳統全覆蓋式通道閘極元件來作多種不同電性比較，進而可證明新高效能假閘極全環繞矽覆絕緣PGAA元件的製程成功率與特性曲線並不輸於傳統全覆蓋式通道閘極GAA元件。

（3）、 將閘極分成上閘極與下閘極兩個部份，如此一來此元件就形成四端元件，借由二個不同的閘極接觸，來提升閘極的控制能力，提升元件的驅動電流和壓抑不理想的效應。

（4）、 新高效能假閘極全環繞矽覆絕緣PGAA元件將比傳統全覆蓋通道式閘GAA的元件製作方式更為簡單，更容易運用在未來元件微小化的製程上，可以改善傳統全覆蓋通道式閘極元件不易蝕刻和填洞的技術節點，可以使元件製作成功率大幅提升，就算是全覆蓋通道式閘極元件使用薄膜電晶體的方式製作，也比新高效能假閘極全環繞矽覆絕緣PGAA元件還要多一道光罩製作挖孔製程，會比較耗損成本。

我們運用模擬製程工具ISE TCAD 9.5預先模擬出多晶矽和單晶矽的新高效能假閘極全環繞矽覆絕緣PGAA元件的結構，來證明此元件製程的可行性，再以TCAD Dessis模擬出來此元件的I-V特性曲線的電性分析。從模擬不同特性曲線之中我們得到個結論：此新高效能假閘極全環繞矽覆絕緣PGAA元件和傳統全覆蓋式通道式閘元件互相作比較後，結果可以看出兩種元件的臨限電壓、次臨界因子幾乎相差不遠，更令人意外的是新高效能假閘極全環繞矽覆絕緣PGAA元件的輸入特性曲線可以看出比較平穩，在Ioff也比較小很多，而且在輸出特性的部份，新高效能假閘極全環繞矽覆絕緣PGAA元件的飽和電流也比較大，也由模擬應證出各種不同結構在主動區膜厚100nm情況下是可以完整消除Kink Effect現象。

因此，新高效能假閘極全環繞矽覆絕緣PGAA（Pseudo-Gate-All-Around）元件元件將比傳統SOI元件結構更適用於未來Low Power和High Speed的超大型積體電路（ULSI）發展。

In this thesis, compared to the conventional pseudo gate all around SOI MOSFET, a similar device is successfully implemented already. This three dimension structure illustrate a pseudo gate all around SOI MOSFET which contains at least four advantages as listed in the following:

(1). Using nearly pseudo gate all around to substitute a conventional single gate structure; in this new design, except the poly-silicon gate formed above the silicon film layer, we further implement a tetragonal-like gate in the beneath, front and back sides of the aforementioned silicon film layer. Such tetragonal-like gate can reach some goals obviously, like better gate controllability and stronger current drive.

(2). The simulation of pseudo gate all around will be compared to a conventional pseudo gate all around by many different electric features to verify that this type of structure should have possibly higher manufacture yield and reliable characteristic.

(3). We can separate the gate into the above gate and the beneath gate to form a four terminals device. By applying different touching electrodes to the two gates, we can bring the gate controllability up, and strengthen the current drive, and suppress some negative effects of the device.

(4). Pseudo gate all around device will be simpler compared to a conventional pseudo gate all around device in the manufacture effort, so it is easier for devices miniaturization in the future, and it can also improve some shortages, like hard-etching and hole-fulfillment, the technical issues in the conventional pseudo gate all arounds device, thus the devices manufacture yield will be brought up greatly, even a conventional pseudo gate all arounds device is applied to thin-film transistor made way, it still needs more one mask for holes plight compared to a pseudo gate all arounds device, it will reflect to the investment.

The simulation tool ISE TCAD is being courtesy of the simulation for pseudo gate all around device structure to verify the feasibility of manufacture and process. And TCAD Dessis is applied to simulate I-V characteristic and other electric analysis. Based on the different curves simulated, we reach the conclusion: put this pseudo gate all around device on the comparison with a conventional pseudo gate all around device, in the following items, threshold voltage, sub-threshold factor are drawn. Incredibly, our design has a flattered input curve and less leakage Ioff, respectively. In the output curve, our work has harvester saturated current and finally, by different structure of simulated result to verify the active region depth may eliminate “kink effect” under 50nm.

Hence, pseudo gate all around SOI MOSFET will be more potentially applied to ULSI (ultra large schematic integrated circuit) in the future, compared to other previous SOI devices.

第一章 緒論-------------------------------------------------------------------------------------9

第二章 模擬結果與討論--------------------------------------------------------------------14

2.1 單一閘極、雙面閘極、三面閘極、全覆蓋通道式閘極、
假閘極SOIMOSFET不同的元件結構作比較--------------------14

2.2 全覆蓋通道式閘極、假閘極全環繞矽覆絕緣SOI MOSFET
元件之多晶矽和單晶矽兩種型式的模擬與比較---------------17

第三章 元件設計與製作--------------------------------------------------------------------29

3.1 製作SOI層----------------------------------------------------------------------29
3.2 製作Back Gate層-------------------------------------------------------------30
3.3 製作Back Gate Spacer------------------------------------------------------32
3.4 沉積Back Gate Oxide與定義出主動區圖形-----------------------33
3.5 製作Front Gate與Front Gate Oxide------------------------------------35
3.6 形成源極跟汲極區域------------------------------------------------------38
3.7 製作Contact Hole------------------------------------------------------------38
3.8 製作金屬層--------------------------------------------------------------------40

第四章 實驗結果與討論-------------------------------------------------------------------44

4.1 半導體元件參數量測說明與注意事項------------------------------45
4.2 IDS－VGS 特性曲線的探討-------------------------------------------------45
4.3 IDS－VDS 特性曲線的探討-------------------------------------------------48
4.4 結論-------------------------------------------------------------------------------50

第五章 結論--------------------------------------------------------------------------------------51


參考文獻-------------------------------------------------------------------------------------------52

[1] S. Veeraraghavan, J.G. Fossum, “Short-Channel Effects in SOI MOSFETs,” IEEE Trans. Electron Devices, Vol. 36, pp. 522-528, March 1989.
[2] H. B. Bakoglu, “Circuits Interconnections and Packaging for VLSI,” Addison Wesley Publishing Company, pp. 38-40, 1990.
[3] J. P. Coling, “Silicon-On-Isolator Technology: Materials to VLSI,” Kluwer Academic Publishers, pp.107-108, 1990.
[4] G. C. Messenger, M. S. Ash, “The Effects of Radiation Electronic System,” Van Nostrand Reinhold Company, pp. 307, 1986.
[5] A. J. Auberton-Herve, “Proceedings of the fourth international Symposium on Silicon-On-Insulator Technology and Device,” Ed. By D.N. Schmidt, Vol. 90-6, pp. 544, 1990.
[6] R. R. Troutman, “Latchup in CMOS Technology,” Kluwer Academic Publishers, 1986.
[7] H. Chenming, “SOI and Device Scaling,” in Proceedings 1998 IEEE International SOI Conference, Oct. 1998.
[8] S. Christoloveanu, and G. Reichert, “Recent Advances in SOI Materials and Device Technologies for High Temperature,” IEEE Trans. Electron Devices, pp. 86-93, 1998.
[9] D. A. Dallmann, K. Shenai, “Scaling Constraints Imposed by Self-Heating in Submicron SOI MOSFET”, IEEE Trans., Vol 42, pp. 489-496, March. 1995.
[10] Y. Apanovich, E. Lyumkis, B. Polsky, P. Blakey, “Non-isothermal analysis of breakdown in SOI transistors,” IEEE Trans. Electron Devices, Vol. 40, pp. 2094–2096, Nov. 1993.
[11] J. Roig, D. Flores, M. Vellvehi, J. Rebollo, J. Millan, “Novel Techniques for Reducing Self-Heating Effects in Silicon On Insulator Power Devices,” Semiconductor Conference, Vol. 2, pp.493–496, Oct. 2001.
[12] B. Cole, S. Parke, “A Methode to Overcome Self-Heating Effects in SOI MOSFETs,” University/Government/Industry Microelectronics Symposium, pp.295- 297, July. 2003.
[13] P. Sivaram, B. Anand, M. P. Desai, “Silicon Film Thickness Considerations in SOI-DTMOS,” IEEE Electron Device Lett., Vol. 23, pp.276-278, May. 2002.
[14] S. Zhang, X. Lin,R. Huang, R. Han, and M. Chan, “A Self-Aligned, Electrically Separable Double-Gate MOS Transistor Technology for Dynamic Threshold Voltage Application,” IEEE Transactions On Electron Devices, Vol. 50, No. 11, Nov.2003.
[15] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora, I. Policicchio, “Floating body effects in polysilicon thin-film transistors,” IEEE Electron Device Lett., Vol. 44, pp.2234–2241, June. 1997.
[16] J. Moers, S. Trellenkamp, A. V. D. Hart, M. Goryll, S. Mantl, P. KordoS, H. Liith., “Vertical p-channel Double-Gate MOSFETs,” IEEE, Sept. 2003.
[17] Y. Li, H. M. Chou, “A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs,” IEEE Trans., Vol. 4, No. 5, Sep. 2005.
[18] X. Zhibin, L. Haitao, Z. Chunxiang, K. Johnny, O. Sin, “A New Polysilicon CMOS Self-Aligned Double-Gate TFT Technology ,” IEEE Trans. Electron Devices, Vol. 52, No. 12, Dec. 2005.
[19] K. Castellani-Coulié, D. Munteanu, J. L. Autran, V. Ferlet-Cavrois, P. Paillet, J. Baggio, “Simulation Analysis of the Bipolar Amplification Induced by Heavy-Ion Irradiation in Double-Gate MOSFETs,” IEEE Trans. Nuclear Science, Vol. 52, No. 6, Dec 2005.
[20] C. Felice, K. Ben, D. Robin, S. Vaidy, S. Purushothaman, S. Eddy, D. Abhisek, J. Malgorzata, G. Guido, “Reliability Comparison of Triple-Gate Versus Planar SOI FETs,” IEEE Trans. Electron Devices, Vol. 53, No. 9, SEPT. 2006.
[21] J. H. Park, O. Kim, “A Novel Self-Aligned Poly-Si TFT With Field-Induced Drain Formed by the Damascene Process,” IEEE Electron Device Lett., Vol. 26, No. 4, APRIL 2005.
[22] Y. C. Woo, Y. S. Jae, D. L. Jong, J. P. Young, B. G. Park, “100-nm n-/p-Channel I-MOS Using a Novel Self-Aligned Structure,” IEEE Electron Device Lett., Vol. 26, No. 4, APRIL 2005.
[23] M. Vinet, T. Poiroux, J. Widiez, J. Lolivier, B. Previtali, C. Vizioz, B. Guillaumot, Y. Le Tiec, P. Besson, B. Biasse, F. Allain, M. Cassé, D. Lafond, J.-M. Hartmann, Y. Morand, J. Chiaroni, and S. Deleonibus, “Bonded Planar Double-Metal-Gate NMOS Transistors Down to 10 nm ,” IEEE Electron Device Lett., Vol. 26, No. 5, May 2005.
[24] P. Y. Kuo, T. S. Chao, R. J. Wang, T. F. Lei, “High-Performance Poly-Si TFTs With Fully Ni-Self-Aligned Silicided S/D and Gate Structure,” IEEE Electron Device Lett., Vol. 27, No 4, APRIL 2006.
[25] B. C. Josephine, W. S. Jeffrey, J. Keith, H. Wilfried, “OFF-State Modulation of SOI Floating-Body,” IEEE Electron Device Lett., Vol. 27, No. 7, July 2006.
[26] H. C. You, P. Y. Kuo, F. H. Ko, T. S. Chao, T. F. Lei,“The Impact of Deep Ni Salicidation and NH3 Plasma Treatment on Nano-SOI FinFETs,” IEEE Electron Device Lett., Vol. 27, No. 10, OC. 2006.
[27] F. Ootsuka', T. Watanabe, Y. Nara', N. Mise, S. Migita, M. Watanabe, H. Satake, A. Toriumi, Onogawa, Tsukuba-shi, “Novel Silicide-Cladded Uniaxially-Strained Thin-Body SOI CMOS FETs Featuring Floating Body Modulation Induced by Hf-based Gate Dielectric,” IEEE International SOI Conference Proceedings, 2006.
[28] B. Jun, M. D. Ryan, L. Qingqing, F. Greg, and D. C. John. D., “Back-Channel, Depletion-Assisted, Gate-Induced Floating Body Effects in Cryogenically-Operated, 90 nm Strained Si SOI MOSFETs ,” IEEE International SOI Conference Proceedings, 2006.
[29] I. C. Cheng, Z. K. Alex, L. Ke, C. S. James, W. Sigurd, “Self-Aligned Amorphous-Silicon TFTs on Clear Plastic Substrates ,” IEEE Electron Device Lett., Vol. 27, No. 3, MARCH 2006.
[30] D. Zhang and M. Wong, S. Member, IEEE.;“Metal-Replaced Junction for Reducing the Junction Parasitic Resistance of a TFT ,” IEEE Electron Device Letters, VOL. 27, NO. 4, APRIL 2006
[31] H. C. Lin, M. H. Lee, K. H. Chang, “Spatially Resolving the Hot Carrier Degradations of Poly-Si Thin-Film Transistors Using a Novel Test Structure ,” IEEE Electron Device Lett., Vol. 27, No. 7, JULY 2006.
[32] J. A. Young, B. J. Cho, H. S. Kang, C. H. Lee, C. Lee, J. m. Yoon, T. Y. Kim, E. S. Cho, S. K. Sung, D. Park, K. K. B. Ryu, “Test Structure for Performance Evaluation of 3 Dimensional FinFETs,” Proc. IEEE 2005 Int. Conference on Microelectronic Test Structures, Vol. 18, April 2005.
[33] S. H. Kim, J. G. Fossum, V. P. Trivedi, “Bulk Inversion in FinFETs and Implied Insights on Effective Gate Width ,” IEEE TRANS. Electron Devices, Vol. 52, No. 9, SEPT. 2005.
[34] Y. X. Liu, K. Endo, M. Masahara, E. Sugimata, T. Matsukawa, K. Ishii, H. Yamauchi,T. Shimizu, K. Sakamoto, S. O'uchi, T. Sekigawa E. Suzuki, “Advanced FinFET Technology: TiN Metal-gate CMOS and 3T/4T Device Integration ,” IEEE International SOI Conference, 2005.
[35] K. H. Cho, S. D. Suk, Y. Y. Yeoh, M. Li, K. H. Yeo,D. W. Kim, S. W. Hwang, D. Park, and B. I. Ryu,“Observation of Single Electron Tunneling and Ballistic Transport in Twin Silicon Nanowire MOSFETs (TSNWFETs) Fabricated by Top-Down CMOS Process,”2006.
[36] J.-P. Colin, M.-H, Gao, A. Romano, H. Maes, and C. Claeys IMEC, Kapeldreef, “Silicon-on-Insulator "Gate-All-Around" MOS Device,” IEEE, 1990.
[37] W. C. Chan, Philip C. H. Chan, “Fabrication of Gate-All-Around Transistors Using Metal Induced Lateral Crystallization,” IEEE Electron Device Lett., Vol. 22, No. 2, FEB. 2001.
[38] R. Cerutti, P. Cwmel, S. Harrisnn, A. Cros, R.Wacque, A Pouydebasque, J.Bustos, S. Borcl, F. Lcvcrd, M. P. Samson, A. Talbot, F.Balcstra, T. Skotnicki, “Metal Gate-All-Around CMOS ihtegration using Poly-gate REplacement Through Contact Hole (PRETCH),” IEEE International Conference on Integrated Circuit and TechnoIogy, 2005.
[39] V. Pott, D. Bouvet, J. Boucart, L. Tschuor, K. E.Moselund, A. M. Ionescu, “Low temperature single electron characteristics in gate-all-around MOSFETs,” IEEE, 2006.
[40] W. W. Fang, N. Singh, L. K. Bera, H. S. Nguyen, S. C. Rustagi, G. Q. Lo, N. Balasubramanian, D.-L. Kwong, “Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors,” IEEE Electron Device Lett., Vol. 28, No. 3, MARCH 2007.
[41] K. H. Yeo, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Cho, K. H. Hong, S. K. Yun, M. S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D. W. Kim, D. Park, and B. I. Ryu;“Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15 nm Length Gate and 4 nm Radius Nanowires,” IEEE, 2006.
[42] L. K. Bera, H. S. Nguyen, N. Singh, T. Y. Liow, D. X. Huang, K. M. Hoe, C. H. Tung, W. W. Fang, S. C. Rustagi, Y. Jiang, G. Q. Lo2, N. Balasubramanian, D. L. Kwong, “Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs,” IEEE, 2006.
[43] T. Ernst, C. Dupré, C. Isheden, E. Bernard, R. Ritzenthaler, V. Maffini-Alvaro, J.-C. Barbé,F. De Crecy, A.Toffoli, C. Vizioz, S. Bore, F. Andrieu, V. Delaye, D. Lafond, G. Rabillé3,J.-M. Hartmann, M. Rivoire, B. Guillaumot, A. Suhm,P. Rivallin,O. Faynot, G. Ghibaudo and S.Deleonibus, “Novel 3D integration process for highly scalable Nano-Beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack,” IEEE, 2006.
[44] N. Singh, F. Y. Lim, W. W. Fang, S. C. Rustagi, L. K. Bera, A. Agarwal, C. H. Tung, K. M. Hoe, S. R. Omampuliyur, D. Tripathi, A. O. Adeyeye1, G. Q. Lo, N. Balasubramanian, D. L. Kwong, “Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance,” IEEE, 2006.
[45] T. Skotnicki, Y.Morand, S.Descombes, P.Coronel, P.Mazoyer, S.Harrison4, P.Ribot, A.Talbot, D.Dutartre, M.Haond, R.Palla, Y.Le Friec, F.Leverd, M-E.Nier, C.Vizioz3, D.Louis3, “50nm - Gate All Around (GAA) - Silicon On INothing (SON) - Devices: A Simple Way to Co-integration of GAA Transistors within bulk MOSFET process,” IEEE, 2002.
[46] W. C. Chan, C. H. Chan, “High performance Gate-All-Around devices using Metal Induced Lateral Crystallization,” IEEE Intemational SOI Conference, Oct. 2000.
[47] J. P. Colinge, A. Terao, “Effects of Total-Dose Irradiation on Gate-All-Around (GAA) Devices,” IEEE TRANS. NUCLEAR SCIENCE, Vol. 40, No. 2, APRIL 1993.