Responsive image
博碩士論文 etd-0824111-172812 詳細資訊
Title page for etd-0824111-172812
論文名稱
Title
設計並實現具可重新組態運算單元之記憶體單元
Design and Implement the Memory Unit with Reconfigurable Computing Unit
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
84
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-19
繳交日期
Date of Submission
2011-08-24
關鍵字
Keywords
軟硬體協同工作、硬體管理單元、可重新組態運算系統
Software-hardware co-work, Hardware Management Unit, Reconfigurable computing system
統計
Statistics
本論文已被瀏覽 5662 次,被下載 1132
The thesis/dissertation has been browsed 5662 times, has been downloaded 1132 times.
中文摘要
可重新組態運算系統在大量資料運算上已被證實具有提昇系統效率的潛力;然而,現今的可重新組態運算的架構大多由中央處理器,搭配一個或多個可重新組態運算單元所組成。但這類型的系統架構,往往會發生System Bus擁擠的現象,在頻寬上便受到限制,降低整體效能。因此本論文提出整合DDRx記憶體與可重新組態運算單元,建構出兼具儲存與運算功能的Brain module。透過DDRx記憶體控制指令的延伸,做為Brain module控制的新指令。並設計Brain module控制器與硬體管理單元,其中以動態建構之硬體管理單元將根據軟硬體協同工作之通訊定義,建立硬體功能召喚機制。並在控制器內建立資料交換機制,來實現軟體資料區與硬體模組的資料傳輸於控制器內部完成,達到降低System Bus負擔與整合式的軟硬體協同工作的目的。在軟體結構上,承襲了傳統程式語言,整合程式資料區與可重新組態運算單元資料區,並透過Memory mapping I/O的方式,進行Brain module資料之取存。讓使用者可以透過整合式的程式設計環境,實現軟硬體協同之工作。
Abstract
It has been confirmed that reconfigurable computing system has potential to accelerate in large amounts of data computing. However, current trend is towards combining a microprocessor with one or many reconfigurable computing units. Thus, it might cause multiple devices to compete for System Bus that caused bus collision. And then the system performance will be limited on the bandwidth. Based on these shortcomings, this paper proposes an architecture which combines DDRx memory with a reconfigurable FPGA to construct a module with both storage and computing functions called Brain module. Brain module’s instruction set is created through the extension of DDRx memory instruction. We also design the brain module controller and Hardware Management Unit. According to the definition of Software-Hardware Co-communication, the dynamically constructed Hardware Management Unit will create a hardware function call mechanism. We also establish internal data switching mechanism to achieve transmission data between memory and reconfigurable computing internal the controller. Thus, it can reduce the workload of System Bus and integrate hardware and software work. In software structure, we inherit the traditional programming language and integrate program data area and reconfigurable computing data area. Brain module data is accessed through memory mapping I/O. User can implement the software-hardware co-work by integrated programming environment,
目次 Table of Contents
摘要 i
ABSTRACT ii
圖次 vii
表次 x
第一章 簡介 1
1-1 研究動機 1
1-2 研究目的 1
1-3 論文架構 2
第二章 相關研究 3
2-1 可重新組態運算系統相關研究 3
2-1.1 Vforce架構 3
2-1.2 STARSoC架構 6
2-1.3 IRES 8
2-2 DDR2相關研究 12
2-2.1 DDR2腳位定義 13
2-2.2 DDR2指令介紹 14
2-2.3 指令時序 16
2-3 FPGA設定方式 17
2-3.1 PS與PPS設定方式 18
2-3.2 PPA設定方式 21
第三章 硬體架構 23
3-1 系統整體架構 23
3-1.1 FPGA command設計 25
3-1.2 FPGA組態電路 28
3-1.3 硬體連線架構 31
3-1.4 加速硬體介面設計 33
3-1.5 硬體管理單元暫存器介紹 36
3-2 Brain 控制器設計 38
3-2.1 控制器架構 39
3-2.2 資料交換機制 42
3-2.3 記憶體定址與規劃 43
3-2.4 FPGA記憶體定址 45
第四章 軟體架構與系統整合 48
4-1 軟體架構 48
4-1.1 硬體函式 49
4-1.2 hardwire_builder 50
4-1.3 dummyOS 52
4-2 系統執行流程 53
第五章 模擬與分析 57
5-1 控制器指令測試 57
5-1.1 初始化 58
5-1.2 單筆寫入與讀取 58
5-1.3 FPGA指令測試 59
5-1.4 多筆寫入與讀取 60
5-2 硬體管理單元測試 61
5-3 Sorting電路硬體設計 62
5-4 整合測試 64
第六章 結論 68
參考資料 69
參考文獻 References
[1] Tsung-chien Ho, “Software-Hardware Interwork Mechanism of FMRPU,” Master thesis, National Sun Yat-sen University, 2007.
[2] Yu-Hsuan Shen, “Design and Implementation of the DDR2 Controller with Data Switching,” Master thesis, National Sun Yat-sen University, 2009.
[3] Ta-Li Yeh, “Design of the Software-Hardware Co-design Platform-IRES,” Master thesis, National Sun Yat-sen University, 2009.
[4] Jih-Ching Chiu, Ta-Li Yeh, and Mun-Kit Leong, “The Software and Hardware Integration Linker for Reconfigurable Embedded System,” IEEE International Conference on Computational Science and Engineering (CSE '09), Vancouver, Canada, Aug. 2009.
[5] Jih-Ching Chiu, Kai-Ming Yang, and Ta-Li Yeh, “A Hardware Invocation Mechanism for Reconfigurable Embedded System,” International Computer Symposium, pp. 664-669, Dec. 2010.
[6] Micron 512Mb SDRAM Data Sheet “MT47H32M16”.
[7] JEDEC DDR2 SDRAM Specification.
[8] Altera Application note 116: Configuring SRAM-Based LUT Devices[S], 2002.
[9] N. Moore, A. Conti, M. Leeser, L.S. King, “Vforce: An Extensible Framework for Reconfigurable Supercomputing,” Computer, March. 2007, pp. 39-49.
[10] D. Buell, T. El-Gbazawi, K. Gaj, V. Kindratenko, “High-Performance Reconfigurable Computing,” Computer, March. 2007, pp. 23-27.
[11] D. Andrews, D. Niehaus, and P. Ashenden, “Programming Models for Hybrid CPU/FPGA Chips,” Computer, Jan. 2004, pp. 118-120.
[12] K. Parnell and R. Bryner, “Comparing and Contrasting FPGA and Microprocessor System Design and Development,” Xilinx Inc., July 2004.
[13] A. Samahi, S. Boukhechem, E. bourennane, “Communication Interface Generation For HW/SW Architecture In The STARSoC Environment,” IEEE International conference on Reconfigurable Computing and FPGA's, IEEE Computer Society Press , San louis Potosi , Mexico, 20 September 2006.
[14] A. Samahi, S. Boukhechem, “Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platforms,” NASA/ESA Conference on Adaptive Hardware and Systems, Edinburgh, United Kingdom, 8 August 2007.
[15] A. Samahi, S. Boukhechem, E. bourennane, N. E. IDIRÈNE, “STARSoC : A C-Based Platform for Rapid Prototyping of Embedded System,” RecoSoC'05, ISBN : 2-9517-4611-3, Montpellier, France, 1 (1), 27 Juin 2005, pp. 177-182.
[16] J.R. Hauser, J. Wawrzynek, “Garp: a MIPS processor with a reconfigurable coprocessor,” FPGAs for Custom Computing Machines, Apr 1997. Proceedings. IEEE Symposium, pp. 12-21.
[17] A. Samahi, S. Boukhechem, “Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platforms,” NASA/ESA Conference on Adaptive Hardware and Systems, Edinburgh, United Kingdom, 8 August 2007.
[18] J.M. Rabaey, “Reconfigurable Processing: The Solution to Low-Power Programmable DSP,” IEEE International Conference on Acoustics, Speech, and Signal Processing, Munich , Germany,1997.
[19] T. Miyamori, K. Olukotun, “REMARC: Reconfigurable Multimedia Array Coprocessor,” Proceedings. ACM/SIGDA FPGA, Feb 1998.
[20] E. Mirsky, A. DeHon, “MATRIX: a reconfigurable computing architecture with configurable instruction distribution and deployable resources,” FPGAs for Custom Computing Machines, Apr 1996. Proceedings. IEEE Symposium, pp. 157-166.
[21] F. Rinnerthaler, W. Kubinger, J. Langer,M. Humenberger,S. Borbely, “Boosting the Performance of Embedded Vision Systems Using a DSP/FPGA Co-processor System,” IEEE International Conference on Systems, Man and Cybernetics, pp.1142–1146, 2007.
[22] E. R. Sousa, J. M. L. Filho, L. G. P. Meloni, “Reconfigurable Hybrid Architectures of Multi-Purpose Based on DSP and FPGA (inportuguese)”, VIII Annual Meeting on Computer, ISSN 2178-6992, October 2010.
[23] U. Meyer-Baese, “Digital Signal Processing with Field Programmable Gate Arrays”, Second Edition, Springer, October 2003.
[24] M. Vuletic, L. Pozzi, and P. Ienne, “Seamless Hardware-Software Integration in Reconfigurable Computing Systems,” IEEE Design & Test of Computers, Mar./Apr. 2005, pp. 102-113.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外完全公開 unrestricted
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available


紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code