本論文研究無接面垂直式電晶體的電性表現，並將其與無接面平面式電晶體和傳統垂直式場效電晶體做比較，分別探討雙閘極架構的優勢，以及無接面電晶體在短通道特性的表現；根據二維模擬結果，無接面垂直式電晶體因為雙閘極架構，相對於平面式電晶體有較好的短通道性能表現，次臨界擺幅和汲極引致能障下降的數據，無接面垂直式電晶體分別為62.04 mV/dec和23.96 mV/V，而無接面平面式電晶體為77.67 mV/dec和146.07 mV/V，證實雙閘極架構有較好的通道控制能力，且無接面垂直式電晶體可製作於矽基板上，更進一步免除使用矽覆絕緣基板所帶來之自我加熱效應，並降低生產成本；另外在無接面垂直式電晶體和傳統垂直式場效電晶體的短通道性能比較中，當柱狀主動區厚度逐漸微縮，傳統垂直式場效電晶體的次臨界擺幅和汲極引致能障下降都是呈現上升的情況，而無接面垂直式電晶體則是呈現下降的情形，說明元件微縮對無接面垂直式電晶體有性能提升的幫助；然而，雖然在射頻�類比等特性方面，無接面垂直式電晶體略輸於傳統垂直式場效電晶體，但無接面垂直式電晶體製程簡單的優點，使其有機會成為未來半導體製程的主流技術。

In this thesis, we carefully investigate the electrical characteristics of junctionless vertical MOSFET (JLVMOS) compared with the junctionless planar MOSFET (JLPMOS) and conversional junction vertical MOSFET (JVMOS). Also, we examine the advantages of the double-gate structure and the short-channel behavior of the junctionless transistors. According to the 2D simulation studies, the proposed JLVMOS can achieve better short-channel characteristics (JLVMOS: 62.04 mV/dec S.S., 23.96 mV/V DIBL; JLPMOS: 77.67 mV/dec S.S., 146.07 mV/V DIBL) as compared with the planar transistor, chiefly owing to the double-gate scheme. This proves that only the double-gate device has better gate controllability over the channel region to reduce the short-channel effect. More importantly is that the JLVMOS has a bulk Si starting material, in which the SOI-induced self-heating effects and the fabrication cost can be well suppressed and reduced, respectively. In comparison with the JVMOS, our proposed JLVMOS exhibits better S.S. and reduced DIBL. Furthermore, although the analog/RF properties of the JLVMOS are somewhat degraded, due to its simple fabrication process, our proposed JLVMOS can become one of the mainstream technology for future CMOS applications.

第一章 緒論 1
1.1 背景 1
1.2 論文回顧 2
1.2.1 垂直式金氧半場效應電晶體 2
1.2.2 無接面金氧半場效應電晶體 5
1.3 結論與動機 10
第二章 元件設計與製程 11
2.1 元件操作原理 11
2.2 FLOOPS TCAD模擬元件理想製程 15
2.3 無接面垂直式電晶體（JLVMOS）實際製程 17
第三章 結果與討論 21
3.1 DESSIS物理模型說明 21
3.2 ISE TCAD模擬軟體DESSIS工具之元件性能分析 23
3.2.1 無接面垂直式和平面式電晶體結果分析 23
3.2.2 無接面和傳統場效垂直式電晶體結果分析 32
3.2.3 下方汲極之無接面和傳統場效垂直式電晶體結果分析 43
3.3 無接面垂直式電晶體實作結果 56
第四章 結論與未來發展 58
4.1 結論 58
4.2 未來發展和應用 58
參考文獻 59
附錄 63
個人著作 63
共同著作 64

[1]S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., New Jersey: Wiley, 2007, p. 507-509.
[2]J. B. Kuo, Member, IEEE, W. C. Lee, and J. H. Sim, “Back-Gate Bias Effect on the Subthreshold Behavior and the Switching Performance in an Ultrathin SOI CMOS Inverter Operating at 77 and 300 K”, IEEE Transactions on Electron devices, vol. 39, no. 12. pp. 2781-2790, December, 1992.
[3]Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, K. Cheng, M. Fujiwara, J. Cai, D. Dorman, S. Mehta, P. Khare, K. Yako, Y. Zhu, S. Mignot, S. Kanakasabapathy, S. Monfray, F. Boeuf, C. Koburger, H. Sunamura, S. Ponoth, A. Reznicek, B. Haran, A. Upham, R. Johnson, L. F. Edge, J. Kuss, T. Levin, N. Berliner, E. Leobandung, T. Skotnicki, M. Hane, H. Bu, K. Ishimaru, W. Kleemeier, M. Takayanagi, B. Doris, R. Sampson, “Ultra-Thin-Body and BOX (UTBB) Fully Depleted (FD) Device Integration for 22nm Node and Beyond”, Symposium on VLSI Technology, pp. 61-62, 2010.
[4]T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. Philip Wong, and F. Boeuf, “THE END OF CMOS SCALING: Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance,” IEEE Circuits and Devices Magazine, vol. 21, no. 1, pp. 16-26, Jan./Feb. 2005.
[5]J. Knoch, M. Zhang, S. Mantl, Member, IEEE, and J. Appenzeller, Senior Member, IEEE, “On the Performance of Single-Gated Ultrathin-Body SOI Schottky-Barrier MOSFETs,” IEEE Transactions on Electron Devices, vol. 53, no. 7, pp. 1669-1674, July 2006.
[6]E. J. Nowak, I. Aller, T. Ludwig, K. Kim, R. V. Joshi, C.-T. Chuang, K. Bernstein, and R. Puri, “TURNING SILICON ON ITS EDGE: Overcoming silicon scaling barriers with double-gate and FinFET technology,” IEEE Circuits and Devices Magazine, vol. 20, no. 1, pp. 20-31, Jan./Feb. 2004.
[7]J.-P. Colinge, C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, no.3, pp. 225-229, March 2010.
[8]H. Liu, Student Member, IEEE, Z. Xiong, and J. K. O. Sin, Senior Member, IEEE, “An Ultrathin Vertical Channel MOSFET for Sub-100-nm Applications,” IEEE Transactions on Electron Devices, vol. 50, no. 5, pp. 1322-1327, May 2003.
[9]H. Cho, P. Kapur, P. Kalavade, and K. C. Saraswat, Fellow, IEEE, “A Low-Power, Highly Scalable, Vertical Double-Gate MOSFET Using Novel Processes,” IEEE Transactions on Electron Devices, vol. 55, no. 2, pp. 632-639, Feb. 2008.
[10]M. M. A. Hakim, L. Tan, O. Buiu, W. Redman-White, S. Hall, and P. Ashburn, “Improved sub-threshold slope in short-channel vertical MOSFETs using FILOX oxidation,” Solid-State Electronics, vol. 53, no. 7, pp. 753-759, July 2009.
[11]A. M. Ionescu, “Nanowire transistor made easy,” Nature Nanotechnology, vol. 5, no. 3, pp. 178-179, March 2010.
[12]J. E. Lilienfeld, “Method and Apparatus for Controlling Electric Currents,” US patent, 1745175, 1925.
[13]Y. Shan, S. Ashok, and S. J. Fonash, “Unipolar accumulation-type transistor configuration implemented using Si nanowires,” Applied Physics Letters, vol. 91, pp. 093518, Aug. 2007.
[14]Y.-W. Lin, Malgorzata M.-Sadowska, W. Maly, A. Pfitzner, and D. Kasprowicz, “Is There Always Performance Overhead for Regular Fabric? ,” IEEE International Conference on Computer Design (ICCD 2008), Oct. 2008, pp. 557-562.
[15]B. Sorée, and W. Magnus, “Silicon nanowire pinch-off FET: Basic operation and analytical model,” International Conference on Ultimate Integration of Silicon (ULIS 2009), March 2009, pp. 245-248.
[16]C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, pp. 053511, Feb. 2009.
[17]C.-W. Lee, A. N. Nazarov, I. Ferain, N. Dehdashti Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J.-P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Applied Physics Letters, vol. 96, pp. 102106, March 2010.
[18]J. R. Davis, A. E. Glaccum, Member, IEEE, K. Reeson, and L. F. Hemment, Member, IEEE, “Improved Subthreshold Characteristics of n-Channel SO1 Transistors,” IEEE Electron Device Letters, vol. 7, no. 10, pp. 570-572, Oct. 1986.
[19]C.-W. Lee, A. Borne, I. Ferain, A. Afzalian, Member, IEEE, R. Yan, N. Dehdashti Akhavan, P. Razavi, and J.-P. Colinge, Fellow, IEEE, “High-Temperature Performance of Silicon Junctionless MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, vol. 3, pp. 620-625, March 2010.
[20]S. M. Sze, and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., New Jersey: Wiley, 2007, p. 28.
[21]S. Gundapaneni, S. Ganguly, Member, IEEE, and A. Kottantharayil, Senior Member, IEEE, “Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling,” IEEE Electron Device Letters, vol. 32, no. 3, pp. 261-263, March 2011.
[22]M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawa, K. Ishii, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki, “Ultrathin Channel Vertical DG MOSFET Fabricated by Using Ion-Bombardment-Retarded Etching,” IEEE Transactions on Electron Devices, vol. 51, no. 12, pp. 2078-2085, Dec. 2004.
[23]H.-S. Philip Wong, K. K. Chan, and Y. Taw, “Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel,” International Electron Devices Meeting Technical Digest. (IEDM 1997), Dec. 1997, pp. 427-430.
[24]D. Hisamoto, Member, IEEE, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, Member, IEEE, C. Kuo, E. Anderson, T.-J. King, J. Bokor, Fellow, IEEE, and C. Hu, Fellow, IEEE, “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, no. 12, pp. 2320-2325, Dec. 2000.
[25]Y. Liu, K. Ishii, T. Tsutsumi, M. Masahara, and E. Suzuki, “Ideal Rectangular Cross-Section Si-Fin Channel Double-Gate MOSFETs Fabricated Using Orientation-Dependent Wet Etching,” IEEE Electron Device Letters, vol. 24, no. 7, pp. 484-486, July 2003.
[26]J.-P. Colinge, C.-W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy, and R. Murphy, “SOI Gated Resistor: CMOS without Junctions,” IEEE International SOI Conference (SOI 2009), Oct. 2009, pp. X-X.
[27]A. Kranti, R. Yan, C.-W. Lee, I. Ferain, R. Yu, N. Dehdashti Akhavan, P. Razavi, and J.-P. Colinge, “Junctionless Nanowire Transistor (JNT): Properties and Design Guidelines,” Solid-State Device Research Conference (ESSDERC 2010), Sep. 2010, pp. 357-360.
[28]C.-W. Lee, A. Afzalian, N. Dehdashti Akhavan, R. Yan, I. Ferain, and J.-P. Colinge, “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, pp. 053511, Feb. 2009.
[29]L. Ansari, B. Feldman, G. Fagas, J.-P. Colinge, and J. C. Greer, “Simulation of junctionless Si nanowire transistors with 3 nm gate length,” Applied Physics Letters, vol. 97, pp. 062105, Aug. 2010.
[30]C.-J. Su, T.-I Tsai, Y.-L. Liou, Z.-M. Lin, H.-C. Lin, Senior Member, IEEE, and T.-S.. Chao, Senior Member, IEEE, “Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels,” IEEE Electron Device Letters, vol. 32, no. 4, pp. 521-523, April 2011.
[31]Y. Sun, H. Y. Yu, N. Singh, K. C. Leong, G. Q. Lo, and D. L. Kwong, “Junctionless Vertical-Si-Nanowire-Channel-Based SONOS Memory With 2-Bit Storage Per Cell,” IEEE Electron Device Letters, vol. 32, no. 6, pp. 725-727, June 2011.
[32]M. Berthomé, S. Barraud, A. Ionescu, and T. Ernst, “Physically-based, multi-architecture, analytical model for junctionless transistors,” International Conference on Ultimate Integration on Silicon (ULIS 2011), March 2011, pp. X-X.
[33]International Technology Roadmap for Semiconductor, 2009. [Online]. Available: http://public.itrs.net
[34]User's Manual, ISE-TCAD, 2004.