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博碩士論文 etd-0826102-153046 詳細資訊
Title page for etd-0826102-153046
論文名稱
Title
在記憶體處理器系統上設計一個新的程式分解機制
The Design of a New Program Decomposition Mechanism for Processor-in-Memory Systems
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
49
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2002-07-26
繳交日期
Date of Submission
2002-08-26
關鍵字
Keywords
程式分解、記憶體處理器
Processor-in-Memory, program decomposition
統計
Statistics
本論文已被瀏覽 5704 次,被下載 1663
The thesis/dissertation has been browsed 5704 times, has been downloaded 1663 times.
中文摘要
近年來,許多研究人員為了要降低中央處理器與記憶體間效能的差距,因此提出了記憶體處理器(Processor-in-Memory)這種新的計算機結構。在先前的研究中,我們針對此種新架構之特性提出了SAGE(Statement Analysis Grouping Evaluation)平行化系統,以充分發揮這種架構的優點。在這篇論文中,我們針對SAGE系統設計一種新的程式分解機制(Program Decomposition Mechanism),此機制根據程式中的控制流程(Control Flow)將其陳述(Statement)做分割(Partition),然後使用Polaris系統分析資料相依關係(Data Dependence Relation),並且產生可讓SAGE系統之工作排程(Task Scheduling)模組排程的加權分割圖(Weighted Partition Dependence Graph)。
Abstract
In recent years, many researchers had proposed a new class of computer architecture, called processor-in-memory (PIM), to reduce the performance gap between the CPU and memory. In order to exploit the benefits of PIM, we designed a parallelizing system – SAGE (Statement Analysis Grouping Evaluation) in our previous research. In this paper, we design a program decomposition mechanism for SAGE system. The mechanism partitions the statements in a program into several parts according to control flow relation. Then it analyzes data dependence relation by using Polaris system, and generates weighted partition dependence graphs which are scheduled by task scheduling mechanisms of SAGE system.
目次 Table of Contents
中文摘要…………………………………………………………………I
英文摘要………………………………………………………………II
目錄……………………………………………………………………..III
圖目錄…………………………………………………………………..IV
表格目錄………………………………………………………………...V
第一章 簡介………………………………………………………….1
第二章 FlexRAM架構介紹…………………………………………3
第三章 SAGE系統介紹……………………………………………….5
第四章 程式分解機制之設計與實作…………………………………8
第4.1節 超區塊圖………………………………………………..8
第4.2節 陳述分割模組…………………………………………11
第4.3節 超區塊圖建構模組……………………………………16
第五章 實驗結果……………………………………………………..37
第六章 結論…………………………………………………………..41
參考文獻………………………………………………………………42
參考文獻 References
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[11] J. R. Allen, D. Callahan, and K. Kennedy, “Automatic Decomposition of Scientific Programs for Parallel Execution,” In Proc. 14th Annual ACM Symposium on the Principles of Programming Languages, 1987.
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[13] Polaris Developer’s Document. Center for Supercomputing Research and Development University of Illinois at Urbana-Champaign, 1995.
[14] K. Faigin, S. Weatherford, J. Hoeflinger, D. Padua, and P. Petersen, “The Polaris Internal Representation,” International Journal of Parallel Programming, Vol. 22, No. 5, 1994.
[15] J. Veenstra, and R. Fowler, “MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors,” in Proc. 2th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, pp. 201-207, 1994.
[16] M. Y. Chen, “The Implementation of Task Evaluation and Scheduling Mechanisms for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering National Sun Yat-Sen University, 2002.
[17] H. J. Jean, “Designing New Scheduling Mechanisms for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering National Sun Yat-Sen University, 2001.
[18] K. E. Hsieh, “The Implementation of Code Generator for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering National Sun Yat-Sen University, 2002.
[19] J. A. McHugh, “Algorithmic Graph Theory,” Prentice-Hall, 1990.
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