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博碩士論文 etd-0826108-052816 詳細資訊
Title page for etd-0826108-052816
論文名稱
Title
一種適用於部分非零輸入有效率的1024點快速傅立葉轉換處理器
A Computationally Efficient 1024-Point FFT Processor with Only a Subset of Non-Zero Inputs
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
59
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2008-07-29
繳交日期
Date of Submission
2008-08-26
關鍵字
Keywords
快速傅立葉轉換、轉換分解
Fast Fourier Transform, Transform Decomposition
統計
Statistics
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中文摘要
快速傅立葉轉換(Fast Fourier Transform)是個有效的分析工具且廣泛的運用在許多的領域上,而一般標準的傅立葉轉換是假設所有固有的輸入和輸出序列是相同的,但實際上,這種假設並不完全精確,在某些情況下只有一些要轉換的輸入是非零的,而其他大部分的輸入為零。本論文中,我們使用一種新的架構,利用轉換分解方法 (Transform Decomposition)的演算法來實現一個1024點的快速傅立葉轉換,當非零輸入為一串連續序列時可有效的降低複雜度。在電路時實現上,我們以MATLAB進行電腦定點數模擬;而硬體實現上則使用Verilog硬體描述語言,設計完成後並以台積電0.18微米標準原件流程(TSMC 0.18 Cell-Based Flow)來完成電路設計。
Abstract
Fast Fourier transformation (FFT) is a powerful analytical tool with wide-ranging applications in many fields. The standard FFT algorithms inherently assume that the length of the input and output sequence are equal. In practice, it is not always an accurate assumption. In certain case only some of the inputs to the transformation function are non-zero but lot of other are zero. In this thesis, a novel architecture of a 1024-point FFT, which adopts the transform decomposition (TD) algorithm, is presented to further reduce the complexity when the non-zero input data are consecutive. To implement this FFT processor, fixed point simulation is a conducted by using MATLB. The hardware implementation is realized by using the Verilog Hardware Description Language (HDL) which is taped out in TSMC0.18 Cell-Based Library for system verification.
目次 Table of Contents
第一章 導論................................................................................................................1
1.0引言..........................................................................................................1
1.1研究動機..........................................................................................................2
1.2論文架構..........................................................................................................2
第二章 快速傅立葉轉換演算法............................................................3
2.0引言.......................................................................................................3
2.1 Decimation-in-Time(DIT)演算法....................................................................3
2.2 Decimation-in-Frequency(DIF)演算法..............................................5
2.2.1 Radix-2 DIF快速傅立葉轉換演算法..................................................5
2.2.2 Radix-4 DIF快速傅立葉轉換演算法..................................................8
2.2.3 Radix-8 DIF快速傅立葉轉換演算法................................................10
2.3 Split-Radix 快速傅立葉轉換演算法................................................11
2.3.1 Radix-2/4 DIF快速傅立葉轉換演算法.............................................12
2.3.2 Radix-2/8 DIF快速傅立葉轉換演算法.............................................13
2.4 Radix-2/4/8快速傅立葉轉換演算法.....................................................14
第三章 部分輸入的快速傅立葉轉換..............................................16
3.0引言................................................................................................................16
3.1轉換分解(Transform Decomposition)的快速傅利業轉換......................16
3.2快速傅立葉轉換複雜度分析..............................................................18
3.2.1標準快速傅立葉轉換複雜度分析.....................................................18
3.2.2轉換分解方法的快速傅立葉轉換複雜度分析.................................21
第四章 硬體架構及硬體實現.................................................................23
4.0引言................................................................................................................23
4.1管線式快速傅立葉轉換硬體架構................................................................23
4.1.1 單一路徑延遲回授架構....................................................................25
4.1.2 多重路徑延遲連接架構....................................................................26
4.2 轉換分解方法的快速傅立葉轉換...............................................................28
4.3 資料輸出序列...............................................................................................32
第五章 系統模擬及合成結果.................................................................................35
5.0引言...............................................................................................35
5.1電路設計流程.......................................................................35
5.2電路模擬結果及晶片規格..............................................................................35
5.2.1 Matlab定點數模擬...............................................................................35
5.2.2 硬體電路模擬...............................................................................37
5.2.2 晶片規格.....................................................................................40
第六章 結論與未來展望..........................................................................................42
中英對照表..................................................................................................................44
全名縮寫對照表..........................................................................................................45
參考文獻.....................................................................................................................46
參考文獻 References
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