隨著醫療技術的發達與社會高齡化，醫療監測設備漸漸演變成微型、低功耗、可攜式為主，而在生醫訊號記錄系統中，類比數位轉換器連接著身體的類比訊號與微處理控制器可使用的數位訊號，方便在監測儀器顯示及觀察醫學上的參數。因此，類比數位轉換器(ADC) 為任何檢測紀錄系統重要組成的一部分，設計一個好的ADC 是非常重要的。本論文設計一類比數位轉換器，利用電壓時間轉換器將類比電壓訊號轉換成一位元的數位輸出訊號，再結合後面的共模差模系統，把單位元輸出轉變為八位元的輸出。而此ADC 利用台積電0.35 μm 製程技術實現於晶片上，面積為726 μm × 630 μm，其量測結果功耗為41 μW，採樣頻率為11.5 KS/s，差分非線性誤差為< 1 LSB，積分非線性誤差為< 1.02 LSB，ADC之FOM 為19.7 pJ/step，此ADC 適用於低功耗生醫記錄系統之應用。

With advances in integrated circuit (IC) processing technology, medical devices are becoming miniature, with low power consumption. Therefore, wearable and implantable applications become feasible, and patients can conveniently monitor their own health parameters. The analog-to-digital converter (ADC) is a crucial building block in such systems, providing the interface between the analog input signals and the digital domain used for signal processing in the microprocessor and by software used to monitor the instrument output. In this thesis, a pair of single-slope integrating ADCs is designed and tested, providing two 8-bit output channels. The ADC channels can be paired on-chip to provide a differential-mode (DM) and common-mode (CM) signal output. The conversion circuit consists of a bias generator, a voltage-to-time converter with comparator, and the digital CM/DM output circuits. The main focus of this thesis is on the design of the voltage-to-time converter circuit and its supporting blocks. Test chips are realized in TSMC 0.35 µm process technology with an active area of 726 μm × 630 μm. The reported measurement results show a power consumption of 41μW, a maximum conversion rate of 11.5 kS/s, differential non-linearity (DNL) below 1 LSB, integral non-linearity (INL) below 1.02 LSB, and a figure-of-merit (FOM) of 19.7 pJ/step, making the design suitable for low-power biomedical application.

致謝 i
摘要 ii
Abstract iii
Contents v
List of Figures vii
List of Tables xii
Chapter 1 Introduction 1
1.1 Background and motivation 1
1.2 Thesis organization 4
Chapter 2 System operation principle 5
2.1 Introduction 5
2.2 ADC specification 8
2.3 System description 9
2.4 Extension to provide CM and DM output 12
Chapter 3 Voltage-to-time converter design 13
3.1 Circuit structure 13
3.2 Bias circuit 14
3.2.1 Selection of bias circuit 14
3.2.2 Internal bias circuit 15
3.2.3 External bias conditioning 20
3.2.4 Current distribution 22
3.3 Low power comparator design 23
3.4 Voltage-to-time converter (VTC) 27
3.5 Circuit layout 32
Chapter 4 Common-mode and differential-mode counters 33
4.1 Common mode block 34
4.2 Differential mode block 37
4.3 Multiplexer outputs 42
Chapter 5 Chip measurement 43
5.1 Testing board 43
5.2 Measurement of bias block 45
5.3 Measurement of VTC 46
5.4 Measurement using ECG signal input 55
5.5 Measurement of CM/DM block 57
5.5.1 Measurement of single ADC output 57
5.5.2 Measurement of DM output 58
5.5.3 Measurement of sign bit 60
5.5.4 Measurement of CM output 60
5.6 Comparison 62
Chapter 6 Conclusion and future works 65
6.1 Conclusion 65
6.2 Future work 66
Reference 67

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