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博碩士論文 etd-0827107-172116 詳細資訊
Title page for etd-0827107-172116
論文名稱
Title
具共振帶間穿隧二極體之金屬氧化半導體元件
A Novel device consisting of MOSFET with Resonance Inter-band Tunneling Diode
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
55
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-16
繳交日期
Date of Submission
2007-08-27
關鍵字
Keywords
共振帶間穿遂二極體、金屬氧化半導體
ritd, mosfet
統計
Statistics
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中文摘要
本論文將共振帶間穿遂二極體與金屬氧化半導體結合做應用,提出一新元件架構,利用所提出元件架構產生閂鎖現象的輸出工作電壓,來感應電場達到控制金屬氧化半導體的切換,提高抗雜訊能力、減少功率消耗、提供高速切換及節省所佔面積等優點。當閘極電壓操作時間較長時,所產生電流工作點因雜訊飄移過大的問題,利用所提出元件的架構來產生閂鎖現象將工作點拑位在兩個穩態點,來提高金屬氧化半導體抗雜訊的能力。由於所提出元件具有較低工作電壓點,能減少功率消耗。在切換過程當中共振帶間穿遂二極體提供高電流密度,能減低迴旋率導致金屬氧化半導體切換速度較慢的因素,提供較高速度切換的金屬氧化半導體。而且所提出元件為堆疊設計,所以可以縮小元件面積,符合未來產品縮小化的趨勢。
Abstract
This thesis focuses on combination of RITD (Resonant Inter-band Tunneling Diode) in MOS (Metal Oxide Semiconductor). Such new device gives architecture, applying to a latch theory and produces a stable, robust output working voltage. This output voltage can induce electric field to control drive current of said MOS. This design can guarantee high noise-defense, reduce power consumption, high speed switch and save space occupation.
When gate voltage has longer slew time, the generated current working point may shift seriously due to noise interference. Importing this new architecture can form latch-phenomenon to keep working point into two stable states robustly, so this design can improve noise-defense ability of MOS. Because the announced device has lower working point voltage, it can reduce power consumption. During switch phase, said RITD can provide high current density to bring low slew rate of a conventional MOS up, thus the high speed switch is reached. Finally, this design of proposed device in this thesis is stack-like shape, then it can cut down space occupation efficiently to match futuristic trend of product profile.
目次 Table of Contents
英文摘要 ………………………………………………………………………… I
中文摘要 ………………………………………………………………………… II
致謝 ……………………………………………………………………………… III
目錄 ……………………………………………………………………………… IV

第一章 導論
1-1 前言 ……………………………………………………………… 1
1-2 負電阻特性說明 ………………………………………………… 2
1-3 共振帶間穿遂二極體說明 ……………………………………… 4
1-4 先前文獻探討 …………………………………………………… 6
1-5 研究動機 ………………………………………………………… 10
第二章 元件設計與實際製程
2-1 元件設計 ………………………………………………………… 11
2-2 元件操作與模擬 ………………………………………………… 14
2-2-1單一元件特性模擬 ……………………………………… 15
2-2-2閂鎖輸出特性模擬 ……………………………………… 17
2-3 實際製程 ………………………………………………………… 19
第三章 元件模擬結果比較
3-1防護電壓比較 …………………………………………………… 23
3-2消耗功率比較 …………………………………………………… 25
3-3製程比較 ………………………………………………………… 26
第四章 結論與未來發展
4-1 結論 ……………………………………………………………… 28
4-2 未來發展 ………………………………………………………… 29

參考文獻 ………………………………………………………………………… 30
附錄 A 實作詳細製程 ………………………………………………………… 32
附錄 B HSPICE 模擬檔 ……………………………………………………… 49
參考文獻 References
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[7] J. P. McKelvey, Solid State Physics for Engineering and Material Science, Krieger Publishing Company, Malabar, Florida, 1993.
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[10] N. Jin, S. Y. Chung, A. T. Rice, and P. R. Berger, R. Yu, P. E. Thompson, R. Lake,“151kA/cm2 peak current densities in Si/SiGe resonant interband tunneling diodes for high-power mixed-signal applications,”Applied Physics Letters, 2003.
[11] N. Jin, S. Y. Chung, R. M. Heyns, P. R. Berger, R. Yu, P. E. Thompson, S. L. Rommel, “Tri-State Logic Using Vertically Integrated Si/SiGe Resonant Interband Tunneling Diodes With Double NDR,” IEEE Electron Device Letters, 2004.
[12] S. Sudirgo, R. P. Nandgaonkar, B. Curanovic, J. L. Hebding, R. L. Saxer, S. S. Islam, K. D. Hirschman, S. L. Rommel, S. K. Kurinec, P. E. Thompson, N. Jin, P. R. Berger,“Monolithically integrated Si/SiGe resonant interband tunnel diode/CMOS demonstrating low voltage MOBILE operation,” Solid State Electronics, vol. 48, pp. 1907-1910, 2004.
[13] D. J. Eaglesham, H. J. Gossmann, and M. Cerullo, “Limiting thickness h for epitaxial-growth and room-temperature Si growth on Si (100),” Phys. Rev. Lett. , vol. 65, pp. 1227–1230, 1990.
[14] H. J. Gossmann, F. C. Unterwald, and H. S. Luftman, “Doping of Si thin-films by low-temperature molecular beam epitaxy,” J. Appl. Phys., vol.73, pp. 8237–8241, 1993.
[15] K. J. Gan, Y. H. Chen, C. S. Tsai and L. X. Su, “Four-valued memory circuit using three peak MOS-NDR devices and circuits,” Electronics Letters 27th, vol.42, no. 9, Apr. 2006.
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