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論文名稱 Title |
使用開關電晶體之低功率與高速度之邏輯合成器
Low Power and High Speed Logic Synthesis with Pass Transistor Logic |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
53 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2001-07-10 |
繳交日期 Date of Submission |
2001-08-28 |
關鍵字 Keywords |
開關電晶體、分段、共享節點、切割 Pass transistor, Partition, Segmentation, Share node |
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統計 Statistics |
本論文已被瀏覽 5648 次,被下載 5341 次 The thesis/dissertation has been browsed 5648 times, has been downloaded 5341 times. |
中文摘要 |
本論文中,我們設計了一個邏輯合成器來合成各種組合電路。輸入為布林函數的格式,可以同時輸入多個函數使電路共享,建立以開關電晶體為主的電路。針對不同的電路特性利用RC delay model與Power model作最佳化,進一步的達到節省面積、提高速度並降低功率消耗。最後輸出為Verilog gate-level code與HSPICE netlist,以提供Verilog-in和模擬使用。 |
Abstract |
In this thesis, a pass-transistor logic synthesizer is developed for logic mapping of any combinational circuits based on only two types of cells: 2-to-1 multiplexors and inverters. The input contains several sum-of-product Boolean function expressions. Our synthesizer will consider the hardware sharing among these Boolean functions in order to save area. The output of our synthesizer is pass-transistor-based circuits with optimized transistor width in terms of user-specified speed and power performance measurement. During optimization, the Elmore RC delay model is used to estimate the critical path delay and the power is characterized by the switching of all the internal nodes. The final outputs are HSPICE netlists and Verilog gate-level code that allow more detailed timing simulation and automatic placement-routing. |
目次 Table of Contents |
目錄 第1章 導論 1-2 1.1 論文架構 1 1.2 動機說明 1-2 1.3 電路特性………………………………………..…………………………………………..…3-9 1.3.1 簡介………………………………………….……………………………………….…….3 1.3.2 CMOS電路……………………………………….……………………………………..3-4 1.3.3 CPL電路……………………………………..……………………………………………..5 1.3.4 DPL電路……………………………………..…………………………………………..6-7 1.3.5 LEAP電路……………………………………….…………………………………………8 1.3.6 PTL 電路……………………………………………………………………………………9 第2章 功率消耗 10-19 2.1 電容估算 10 2.1.1 MOS電容特性 10-11 2.1.2 MOS元件電容 11 2.1.3 擴散電容 12 2.2 靜態功率消耗 13-14 2.2.1 功率消耗 13-14 2.2.2 SWITCHING PROBABILITY 15-17 2.2.3 VOLTAGE SWING 18-19 第3章 最佳化 20-38 3.1 簡介 20 3.2 RC DELAY與POWER CONSUMPTION 21 3.3 電晶體寬度選擇 22-26 3.4 切割 27-38 3.4.1 簡介 27-28 3.4.2 切割在實作上的考量 ……………………………………………………………..…29-36 3.4.3 切割路徑的選擇 37 3.4.4切割後的功率與RC DELAY的考量 38 第4章 邏輯合成器 39-44 4.1 簡介 39 4.2 邏輯合成流程 39-42 4.3 相關軟體工具使用流程……………………………..………………………………………43-44 第5章 結果比較 45-48 第6章 結論與未來工作 49 第7章 參考文獻 50-51 |
參考文獻 References |
第七章 參考文獻 [1] J. S. Yeh, Logic/Circuit synthesizer Based on High Performance Pass-Transistor Cell Library, July 1998 [2] D. Y. Chen, Logic/Circuit synthesizer Based on Low-Complexity Pass-Transistor Cell Library, Aug. 1999 [3] C.C Hsu, Automatic Optimization in Pass-Transistor-Based Logic Synthesizer, July 2000 [4] Wayne Wolf, Modern VLSI Design a System Approach. [5] K.Yano, Y.Sasaki, K.Rikino,and k.Seki “ Top-down pass-transistor logic d esign”, IEEE JSSC,vol.31,no.6,pp.792-803,June.1996 [6] Abdellatif Bellaouar and Mohamed I. Elmasry,“Low-power Digital VLSI Design Circuit and System”, Boston : Kluwer Academic Publishers, c1995 [7] Gray K. Yeap, Ph.D. Practical Low Power Digital VLSI Design. Boston, Mass. : Kluwer Academic Publishers, c1998 [8] Neil H.E. Weste/Kamran Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective 2/E [9] Yi-Yu Liu, “Low Power Driven Pass Transistor Logic Synthesis by Binary Decision Diagrams”, July 2000 [10] Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou, ”A Structure-Oriented Power Modeling Technique for Macrocells,” IEEE Trans. On VLSI Systems, vol. 7 No.3, pp. 380~391, September 1999 [11] Thomas K. Callaway, Earl E. Swartzlander, Jr. “Power-Delay Characteristics of CMOS Multipliers,” 1997,Proceedings,13th IEEE Symposium on,1997 pp.26-32 [12] K. Yano, T. Yamanaka, T. Nishida. M. Saito, K. Shimohigashi, and Shimizu, “ A 3.8 ns CMOS 16X16 multiplier using complementary pass-transistor logic,” IEEE JSSC, pp. 388-395, Apr. 1990. [13] M. Suzuki, N. Ohkubo, T. Yamanaka. A. Shimizu, and K. Sasaki, ”A 1.5 ns 32 b CMOS ALU in double pass-transistor logic,” IEEE JSSC, pp. 1145-1150, Nov. 1993 [14] K.Yano, Y.Sasaki, K.Rikino,and k.Seki , “Top-down pass-transistor logic d esign,” IEEE JSSC, vol. 31, No. 6, pp. 792-803, June. 1996 [15] Theodoridis, G.; Theoharis, S.; Soudris, D.; Goutis, C. ”Switching activity estimation under real-gate delay using timed Boolean functions,” Computers and Digital Techniques, IEE Proceedings- , Volume: 147 Issue: 6 , Nov. 2000 [16] Stroobandt, D.; Verplaetse, P.; van Campenhout, J. “Generating synthetic benchmark circuits for evaluating CAD tools ,“ Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , Volume: 19 Issue: 9 , Sept. 2000 , pp.1011 –1022 |
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