本篇論文提出了一個適用於多碼率並且符合IEEE 802.16e標準的低密度同位檢查碼（Low-Density Parity-Check code，LDPC）解碼器。為了支援此標準不同碼率的檢查矩陣，本篇論文提出了一個以邊序列化（edge-serial）執行的可程式化LDPC解碼器。此架構能夠根據內部一連串的更新指令執行序列化的檢查節點運算。當每個檢查節點相連的位元節點數在一定的範圍之內時，任何複雜或是非正規檢查矩陣都能適用於此架構。除了具有高度的使用彈性外，本篇論文也提出了幾個適用於LDPC解碼器的最佳化技巧。首先，在過去LDPC解碼器的相關研究都著重在檢查節點的運算。本篇論文則提出了另外一種以位元節點運算為主的執行方式，此種執行方式可以使得設計更精簡化。第二，使用一種更好、更快速的訊號更新方式，此種方式可以讓訊號收斂所需的時間縮短。除此之外，更能夠節省大約一半的訊號儲存硬體。更進一步的，當使用位元節點為主的執行方式時，可以利用提早停止機制（early termination）達到停止部分位元節點的運算進而減少解碼的時間。其他設計的特色還包括重新排程訊號執行的順序，使得相鄰的遞迴運算週期（iteration）可以重疊執行，避免因為內部管線化（pipeline）後的訊號延遲（latency）所可能造成的訊號更新問題。透過這些提出的最佳化方法，我們的實驗結果為硬體成本可以節省大約23.1%，解碼時間可以節省約27.4%。使用0.18 µm製程合成後的邏輯閘數（gate count）為316k。實驗的數據顯示本篇論文提出的LDPC解碼器可以達到235 MHz的工作頻率，並且提供平均約116 Mbps的吞吐量（Throughput）效能。

This thesis presents a novel VLSI design of multi-code rate Low-Density Parity-Check code (LDPC) decoder for IEEE 802.16e standard. In order to support the different code rates adopted by the standard, this thesis proposes a programmable LDPC decoder architecture based on the edge-serial approach. This edge-serial architecture can perform the sequential check-node computation according to the internal sequence update commands. Any complex and irregular parity-check matrix can all be realized in the proposed architecture if the number of bit-nodes each check node connects does not exceed a certain bound. In addition to the high flexibility, this thesis also proposes several design optimization techniques suitable for the LDPC decoder. First, the designs of the LDPC decoders in the past all put more emphasis on the realization of check node function. This thesis instead applies a novel bit-node major approach which can lead to more compact design. Secondly, a fine-grain message update method is used which allows more rapid message passing such that the decoder can converge in less cycles. In addition, almost half of the message memory can be reduced. Furthermore, based on the bit-node major decoder design, the early termination scheme can be utilized to partially terminate the function of some bit nodes to reduce the decoding cycles. The other salient features also include the rescheduling of the message update order to allow the overlap of different decoding iterations in order to reduce effect of the possible message update hazard due to the long internal pipeline latency. Based on the proposed optimization methods, our experimental results show that the hardware cost can be reduced by 23.1% while the decoding cycles can be reduced by 27.4%. The proposed LDPC decoder
architecture has been realized by using 0.18 µm technology with the total gate count of 316k. Our experimental shows that the proposed LDPC decoder can run up to 235 MHz and deliver the average of 116 Mbps throughput.

第1章 導論 13
第1.1節 研究背景與動機 13
第1.2節 論文組織 14
第2章 低密度同位檢查碼 16
第2.1節 低密度同位檢查碼簡介 16
第2.2節 低密度同位檢查碼在IEEE 802.16e標準之資訊 19
第3章 編碼方法與解碼演算法 22
第3.1節 編碼方法簡介 22
第3.2節 常用解碼演算法簡介 26
第3.2-1節 Sum-of-Product Algorithm（SPA）27
第3.2-2節 Minimum-Sum Algorithm（MSA）27
第3.2-3節 Forward-Backward Algorithm（FBA）28
第3.3節 解碼演算法錯誤率與檢查節點硬體比較 29
第4章 解碼器架構 33
第4.1節 平行化架構（Parallel Architecture）33
第4.2節 序列化架構（Serial Architecture）33
第4.3節 本設計之架構 34
第4.3-1節 整體基本架構 34
第4.3-2節 檢查矩陣相關資訊編碼 36
第4.3-3節 移位運算架構 37
第4.3-4節 檢查節點架構 38
第4.3-5節 位元節點架構 38
第5章 量化 40
第6章 不同執行節點之效能探討 42
第6.1節 整體架構比較 42
第6.2節 硬體需求比較 44
第7章 不同訊號更新方式之效能探討 48
第7.1節 解碼時間影響 49
第7.2節 硬體架構影響 52
第7.3節 硬體需求影響 57
第8章 提早停止解碼機制之探討（Early Termination，ET）59
第8.1節 目前已提出之提早停止解碼機制簡介 59
第8.2節 本設計之提早停止解碼機制 61
第8.2-1節 位元節點提早停止機制（Bit-Node Early Termination）61
第8.2-2節 檢查節點提早停止機制（Check-Node Early Termination）63
第8.3節 提早停止解碼機制之效能探討 65
第8.3-1節 以檢查節點為主之效能 66
第8.3-2節 以位元節點為主之效能 68
第8.3-3節 使用單一記憶體與提早停止機制之效能分析 69
第9章 結論 70
REFERENCE 74

[1] IEEE 802.16e-2005, “IEEE Standard for Local and Metropolitan Area Network – Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems – Amendment 2: Physical and Medium Access Control layers for Combined Fixed and Mobile Operation in Licensed Bands,” 2005.
[2] C. Berrou, A. Glavieux, and P. Thitimajshima, “Near Shannon limit error-correcting coding and decoding: Turbo codes,” in Proc. Int. Conf. Communications (ICC’93), Geneva, Switzerland, pp.1064–1070, May 1993.
[3] D. J. C. MacKay and R. M. Neal. “Good codes based on very sparse matrices,” in Proc. 5th IMA Conference, Springer, Berlin, number 1025 in Lecture Notes in Computer Science, pp. 100-111, 1995.
[4] Sae-Young Chung, G. David Forney Jr., Thomas J. Richardson and Rudiger Urbanke, “On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit,” IEEE Communications Letters, vol. 5, no. 2, pp. 58-60, Feb. 2001.
[5] R. G. Gallager, “Low Density Parity Check Codes,” IEEE Transactions on Information Theory, vol. 8, no. 1, pp.21-28, Jan. 1962.
[6] F. R. Kschischang, B. J. Frey, and H.-A. Loeliger, “Factor graphs and the sum-product algorithm,” IEEE Trans. Inform. Theory, vol. 47, pp.498–519, Feb. 2001.
[7] M. Fossorier, M. Mihaljevic, H. Imai, “Reduced complexity iterative decoding of low-density parity check codes based on belief propagation,” IEEE Trans. on Commun., vol. 47, no. 5, pp. 673-680, May 1999.
[8] L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linear codes for minimizing symbol error rate,” IEEE Trans. Inform. Theory, vol. 20, pp. 284–287, Mar. 1974.
[9] P. Roberston, E. Villebrun, and P. Hoeher, “A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain,” in Proc. IEEE Int. Conf. Communications, vol. 2, pp. 1009–1013, June 1995.
[10] J. Hagenauer, E. Offer, and L. Papke, “Iterative decoding of binary block and convolutional codes,” IEEE Trans. Inform. Theory, vol. 42, pp. 429-445, Mar. 1996.
[11] X. Y. Hu, E. Eleftheriou, D. M. Arnold, and A. Dholakia., “Efficient implementations of the sum-product algorithm for decoding LDPC codes,” in Proc. IEEE GLOBECOM, San Antonio, TX, vol. 2, pp. 1036–1036E, 2001.
[12] E. Eleftheriou, T. Mittelholzer, and A. Dholakia, “Reduced-complexity decoding for low-density parity-check codes,” IEEE Electron. Lett., vol. 37, pp. 102–104, Jan. 2001.
[13] A. Anastasopoulos, “A comparison between the sum-product and the min-sum iterative detection algorithms based on density evolution,” in Proc. IEEE Globecom, San Antonio, TX, pp. 1021–1025, Nov. 2001.
[14] A. Blanksby and C. J. Howland, “A 220mW 1-Gbit/s 1024-Bit Rate-1/2 Low Density Parity Check Code Decoder,” in Proc. IEEE CICC, LasVegas, NV, USA, pp. 293-6, May 2001.
[15] A. Blanksby and C. J. Howland, “A 690mW 1-Gbit/s 1024-b Rate-1/2 Low -Density Parity-Check Code Decoder,” IEEE Journal of Solid-State Circuits, vol. 37, no. 3, pp. 404-412, March 2002.
[16] M. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-Bit Programmable LDPC Decoder Chip,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 684-698, March 2006.
[17] Engling Yeo, Borivoje Nikolic, and Venkat Anantharam, “Architectures and Inplementations of Low-Density Parity Check Decoding Algorithms,”Circuits and Systems, vol. 3, pp. III-437-III-440, Aug. 2002.
[18] M. M. Mansour and N. R. Shanbhag, “Low-Power VLSI Decoder Architecture for LDPC Codes,” Low Power Electronics and Design, 2002. ISLPED’02, pp. 284-289, 2002.
[19] M. M. Mansour and N. R. Shanbhag, “Turbo decoder architectures for low-density parity-check codes,” in Proc. IEEE GLOBECOM, Taipei, Taiwan, R.O.C., pp. 1383–1388, Nov. 2002.
[20] M. M. Mansour and N. R. Shanbhag, “Architecture-Aware Low-Density Parity-Check Codes,”Circuits and Systems, 2006.ISCAS’03. Proceedings of the 2003 International Symposium on, vol. 2, pp. II-57 - II-60, May 2003.
[21] Tsung-Han Tsai and Cheng-Hung Lin, “A low complexity channel estimation algorithm and architecture design in turbo codes with early termination techniques,” Emerging Technologies: Frontiers of Mobile and Wireless Communication, 2004. Proceedings of the IEEE 6th Circuits and Systems Symposium on, vol. 1, pp. 213-216, 2004.
[22] Richard Bresnan, William Marnane, and Massimiliano Sala, “Efficient low-density parity-check decoding,” ISSC, Belfast, Ireland, June 2004.
[23] Brack T., Alles M., Kienle F., and Wehn N., “A Synthesizable IP Core for WIMAX 802.16E LDPC Code Decoding,” Personal, Indoor and Mobile Radio Communications, 2006 IEEE 17th International Symposium on, pp. 1-5, Sept. 2006.