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博碩士論文 etd-0828110-112834 詳細資訊
Title page for etd-0828110-112834
論文名稱
Title
嵌入式系統之AXI匯流排協定檢測器
Embedded On-chip Protocol Checker for AXI
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
197
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-05-14
繳交日期
Date of Submission
2010-08-28
關鍵字
Keywords
匯流排、晶片整合、驗證、協定
Protocol, Debug, Bus, Integrated
統計
Statistics
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中文摘要
隨著 SoC 的設計越來越複雜,整合者在整合的工作上遇到的問題也越來越多、越來
越複雜。所以傳統的設計經驗已經漸漸的無法符合現今複雜SOC 的要求,所以重新使
用(reuse)的觀念也是越來越重要。當系統晶片整合者將不同的IP 整合到一個環境中時,
若這些IP 都已經經過完整驗證,則可以加快整個系統驗證的時間,但由每個IP 設計者設
計電路的觀念不盡相同,選擇訊號傳輸的方式也可能有所差異,所以整合系統時可能會遇
到原先各IP 設計沒想到的問題發生,在這個時候我們就需要一個協定檢測器去檢測每
一筆的傳輸是否合乎匯流排傳輸協定。傳統以模擬為主的協定檢測模組可以檢測出匯流
排上的訊號是否符合匯流排協定,但他們是不可合成的,所以無法即時的在實際的硬體環
境檢測匯流排上的所有傳輸是否發生協定上的錯誤。所以我們實做了一個rule-based 且
可合成的AXI(Advanced eXtensible Interconnect)匯流排協定檢測器(AXIChecker)來幫助
整合者檢查硬體在傳輸時是否發生違反協定的錯誤行為。
Abstract
In the recent year, System-on-Chip (SoC) has become a popular and important issue. As
the environment of the SoC design becomes more and more complex. The issue of system
verification becomes more important. In previous, the intellectual property (IP) was
developed dependently. Every designer just designed the IP without integrated with others.
But with the complexity of the environment increasing, more and more IPs are integrated into
a system. Even though the verification plans are more complex, but some protocol errors can
also not found by designers. Some incautious behavior may cause the system deadlock or in a
jam. Some research use protocol checker to verify bus protocol, but they can’t synthesize, so
we propose a rule-based and synthesizable style protocol checker(AXIChecker) to verify the
transactions on the AXI bus conform the AMBA 3.0(AXI) protocol or not.
目次 Table of Contents
CHAPTER 1. INTRODUCTION .................................................................................................................... 1
1.1 BACKGROUND ..................................................................................................................................... 1
1.2 MOTIVATION ........................................................................................................................................ 1
1.3 RESEARCH METHOD .............................................................................................................................. 2
1.4 CONTRIBUTION .................................................................................................................................... 2
1.5 THESIS ORGANIZATION ......................................................................................................................... 2
CHAPTER 2. RELATED WORK ................................................................................................................... 4
2.1 FORMAL MODELING AND SYMBOLIC VERIFICATION ............................................................................... 4
2.2 MONITOR-BASED CHECKER .................................................................................................................. 6
CHAPTER 3. AMBA AXI INTRODUCTION ............................................................................................. 10
3.1 AXIMASTER MODULE ....................................................................................................................... 10
3.1.1 AXI master interface...................................................................................................................... 10
3.1.2 AXI master output signal list ......................................................................................................... 12
3.1.3 Handshake process ........................................................................................................................ 14
3.1.4 Lock type ...................................................................................................................................... 16
3.1.5 AXI master related rule ................................................................................................................. 17
3.2 AXI SLAVE MODULE ........................................................................................................................... 18
3.2.1 AXI slave interface ........................................................................................................................ 18
3.2.2 AXI slave response type ................................................................................................................. 20
3.2.3 AXI slave related rules .................................................................................................................. 21
3.3 DEFAULT SLAVE ................................................................................................................................. 22
3.4 INTRODUCTION OF BASIC AMBAAXI TRANSFER ............................................................................... 22
3.5 COMPARE BETWEEN AHB AND AXI .................................................................................................... 23
3.5.1 Separate channel ........................................................................................................................... 23
3.5.2 Burst address issue ........................................................................................................................ 23
3.5.3 Multiple outstanding address issue ............................................................................................... 23
3.5.4 Out-of-order transaction completion............................................................................................. 23
3.5.5 Hardware cost ............................................................................................................................... 24
CHAPTER 4. AMBA AXI PROTOCOL CHECKER ................................................................................. 25
4.1 AXICHECKER ARCHITECTURE ............................................................................................................ 25
4.1.1 Protocol Checking Module ............................................................................................................ 26
4.1.2 Error Reference Table ................................................................................................................... 30
4.2 HISTORY MEMORY .............................................................................................................................. 31
4.3 CONFIGURATION REGISTER ................................................................................................................. 32
4.4 AXICHECKER ANALYZER ................................................................................................................... 33
4.5 REDUCE HARDWARE COST .................................................................................................................. 34
4.5.1 Resource sharing ........................................................................................................................... 34
4.5.2 How do the number of masters and slaves affect the cost? ........................................................... 36
4.6 APPLY AXICHECKER FOR CROSSBAR AND SHARE-LINK BUS TYPE ....................................................... 37
4.6.1 Apply AXIChecker in share-link bus type ...................................................................................... 37
4.6.2 How to connect AXIChecker to share-link AXI interconnect ......................................................... 38
4.6.3 How to setup configuration register of AXIChecker and read error reference table of AXIChecker
40
4.6.4 Apply AXIChecker in crossbar AXI interconnect .......................................................................... 41
4.6.5 How to connect AXIChecker to AXI Agent .................................................................................... 45
4.6.6 How to setup configuration register of AXI Agent ........................................................................ 45
4.7 THE DIFFERENCE BETWEEN AXICHECKER AND HPCHECKER ............................................................. 47
4.7.1 The rule difference between HPChecker and AXIChecker ............................................................ 47
4.7.2 The challenge of AXIChecker ........................................................................................................ 50
CHAPTER 5. VERIFICATION STRATEGY FOR AXICHECKER ........................................................ 53
5.1 RTL VERIFICATION .............................................................................................................................. 54
5.1.1 Using an Synopsys’ VIP to Verify AXIChecker .............................................................................. 54
5.1.2 Problem of Synopsys VIP .............................................................................................................. 55
5.1.3 Using Fault Generator to generate error bus signals ................................................................... 57
5.2 FPGA VERIFICATION ........................................................................................................................... 58
5.2.1 Using Fault Generator to generate error bus signals ................................................................... 59
5.3 CODE COVERAGE ............................................................................................................................... 62
CHAPTER 6. EXPERIMENT RESULTS .................................................................................................... 64
6.1 CASE STUDY 1: 3D GRAPHICS SOC ENVIRONMENT ............................................................................. 66
6.1.1 3D graphics SoC case study result ................................................................................................ 67
6.2 CASE STUDY 2: JANUS-I SOC .............................................................................................................. 68
6.2.1 Janus-I SoC case study result 1 ..................................................................................................... 69
6.2.2 Janus-I SoC case study result 2 ..................................................................................................... 71
6.2.3 Janus-I SoC case study result 3 ..................................................................................................... 71
6.2.4 Janus-I SoC case study result 4 ..................................................................................................... 72
6.2.5 Janus-I SoC case study result 5 ..................................................................................................... 73
6.3 SYNTHESIS RESULT ............................................................................................................................. 74
CHAPTER 7. CONCLUSION ....................................................................................................................... 75
CHAPTER 8. FEATURE WORK ................................................................................................................. 76
REFERENCE ..................................................................................................................................................... 77
APPENDIX A: AXICHECKER RULES DETAIL INTRODUCTION .......................................................... 79
APPENDIX B: SCHEMATIC OF TSMC 0.18MM PROCESS 1.8-VOLT SAGE-X STANDARD CELL
........................................................................................................................................................................... 179
APPENDIX C: HOW TO DUMP ERROR REFERENCE TABLE OF AXICHECKER IN OS
ENVIRONMENT .............................................................................................................................................. 184
APPENDIX D: SETUP SYNOPSYS VIP ENVIRONMENT ........................................................................ 186
D.1 HOW TO CREATE VIP ENVIRONMENT? ................................................................................................ 186
D.2 HOW TO CONNECT DUT(DESIGN UNDER TEST) TO VIP ENVIRONMENT? .......................................... 186
D.3 HOW TO RUN SIMULATION ON VIP ENVIRONMENT? ........................................................................... 187
D.4 HOW TO USE THE VIP WAVEFORM VIEWER? ....................................................................................... 187
參考文獻 References
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[12] Hue-Min Lin; Chia-Chih Yen; Che-Hua Shih; Jing-Yang Jou. “On compliance test of on-chip bus for SOC ”. Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004.
[13] Synopsys. “Using the DesignWare Verification Models for the AMBA 3 AXI Protocol”, April, 2009.
[14] ARM. “AMBA 3 AXI Protocol Checker v1.0 User Guide”, April, 2006.
[15] Chien-Chou Wang. “AHB On-Chip Bus Protocol Checker”, December, 2007.
[16] Wen-Chi Shiue. “An Embedded Multi-Resolution AMBA Trace Analyzer/Debugger for SOC Development”, April, 2007.
[17] L.-B. Chen, R.-T. Gu, W.-S. Huang, C.-C. Wang, W.-C. Shiue, T.-Y. Ho, Y.-N. Chang, S.-F. Hsiao, C.-N. Lee, and I.-J. Huang, “An 8.69 Mvertices/s 278 Mpixels/s Tile-based 3D Graphics SoC HW/SW Development for Consumer Electronics,” Proc. IEEE/ACM 14th Asia and South Pacific Design Automation Conference (ASP-DAC’09), 2009.
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