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論文名稱 Title |
鉿摻雜氧化矽薄膜之電阻切換機制研究 Study On Resistive Switching Mechanism Of Hafnium-doped Silicon Oxide Thin Film |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
125 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2012-07-13 |
繳交日期 Date of Submission |
2012-08-28 |
關鍵字 Keywords |
物理機制模型、氧化矽、鉿、摻雜、一級反應、元件可靠度 doped SiO2, physical mechanism, double layer structure, hydrogen plasma treatment, Hf |
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統計 Statistics |
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中文摘要 |
本論文主要研究在氧化矽中微量摻雜過鍍金屬鉿並且應用在以TiN當作下電極;Pt當作上電極的結構中製作出具有電阻切換特性之電阻式記憶體元件,且元件可在DC模式下操作100次並在常溫下經過一萬秒後依然可保持良好的記憶特性。 本研究利用雙層結構在主動層(Hf:SiO2)下方靠近下電極TiN端製造一富N之轉換層(Hf:SiO2(摻雜N2與NH3))其結構為Pt/Hf:SiO2/Hf:SiO2(摻雜N2與NH3)/TiN。此種元件結構之電阻切換特性會因轉換層富N而有特別好的儲存氧離子功能,且因為通NH3氣導致在轉換層有H電漿處理的效果,使得元件之在轉換層與下電極間之界面效應會特別明顯,因此可以使I-V特性曲線有明顯的變化,利用這樣的變化我們可以製作出有multi-bit功能之電阻式記憶體,且在元件可靠度的測試均有良好的表現;並且利用Current-Voltage Fitting並利用材料分析來佐證所提出之物理機制模型。 本研究利用Ti/HfO2/TiN的結構做給一定電壓使元件發生Reset反應的量測方式(Constant Voltage Sampling)取得其電流與時間之關係,經過數學計算後得到其LnQ對時間之關係,並利用化學反應級數公式驗證Reset反應為一級化學反應,並且萃取出其斜率K值,而後利用在不同溫度條件下萃取出之K值經自然對數轉換後(LnK)對溫度倒數(1/T)做圖,取其斜率萃取出活化能Ea且根據文獻【36】、【37】、【38】,進而探討Reset過程中發生之所有事件並提出一個Reset process所經歷的步驟。 |
Abstract |
In this study,The bottom electrode(TiN),middle insulator(Hf:SiOx),and top electrode(Pt) were deposited respectively by sputtering technique for fabricating the RRAM with MIM structure.The mole fraction of hafnium were about 5%.Instead of non-doped SiO2 base device has no switching characteristic,the Hf-doped SiO2 RRAM could be operator over 100 times and resistive state was kept stable over 104 second. In this researches,the double layer structure(Pt/Hf:SiO2/Hf:SiO2(doped N2 and NH3)).The Resistance switching characteristics of double layer structure device has particular I-V characteristics due to the doping of N.The doping of NH3 cause hydrogen plasma treatment on double layer device also bring about particular I-V characteristics. The physical mechanism we had proposed were proof by the Current-Voltage fitting and the material analysis.By control stop-voltage,the double layer structure device can operation by multi-bit. The detail physical mechanism is studied by the stable RRAM device(Ti/HfO2/TiN).In this study,the model of reset process we had proposed were proof by the special measurement methods(Constant-voltage sampling) and the principle of chemical reaction mechanism. |
目次 Table of Contents |
目錄 摘要 i Abstract ii 致謝 iv 目錄 vi 圖目錄 ix 表目錄 xii 第一章 緒論 1 1.1 前言 1 1.2 研究目的與動機 2 1.3 次世代非揮發性記憶體 3 1.3.1 鐵電式隨機存取記憶體(FeRAM) 3 1.3.2 相變化記憶體(PCRAM) 【8】 3 1.3.3 磁阻式記憶體(MRAM) 4 1.3.4 電阻式記憶體(RRAM) 5 1.4 電阻式記憶體材料 6 1.4.1 鈣鈦礦 6 1.4.2 高分子材料 8 1.4.3 過渡金屬氧化物 8 1.5 電阻式記憶體切換機制 9 1.5.1 阻絲模型 9 1.5.2 焦耳熱效應 10 1.6 陽離子遷移 11 1.7 絕緣體載子傳導機制【27】 12 1.7.1 歐姆傳導(Ohmic Conduction) 【27】 13 1.7.2 穿隧(Tunneling) 【27】 13 1.7.3 蕭基發射(Schottky emission) 【27】 13 1.7.4 普爾-法蘭克發射( Poole-Frenkel emission ) 【27】 14 1.7.5 空間電荷限制電流(Space Charge limit current, SCLC) 【27】 16 第二章 實驗設備介紹 17 2-1 材料分析設備 17 2.1.1 傅立葉轉換紅外光譜儀(Fourier-Transform Infrared Spectrometer) 【28】 17 2.1.2 X光電子能譜(XPS) 19 2.2 製程設備 20 2.2.1 多靶磁控濺鍍系統(Multi-Target Sputter) 【29】 20 2.3 電性量測設備 21 2.3.1 半導體精準電性量測系統 21 第三章 鉿摻雜氧化矽薄膜電阻式記憶體(Hf:SiOx RRAM) 23 3.1 Pt/SiOx/TiN 23 3.1.1 Pt/SiOx/TiN元件製備 23 3.1.2 Pt/SiOx/TiN 元件I-V特性 27 3.2 Pt/Hf:SiOx/TiN 29 3.2.1 Pt/Hf:SiOx/TiN 元件製備 29 3.2.2 Hf:SiOx 材料分析 31 3.2.3 Pt/Hf:SiOx/TiN 元件I-V特性 35 第四章 雙層結構Pt/Hf:SiOx/ Hf:SiOx (摻雜N2與NH3) / TiN RRAM 38 4.1 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)TiN 38 4.2 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)/TiN 元件製備 38 4.3 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)/TiN 材料分析 42 4.3.1 傅立葉轉換紅外線光譜(FTIR) 42 4.3.2 X光線電子能譜(XPS) 44 4.4 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)/TiN元件I-V特性 48 4.4.1 停止電壓(Stop voltage)較Set voltage低 51 4.4.2 停止電壓(Stop voltage)為Set voltage 51 4.4.3 停止電壓(Stop voltage)較Set voltage高 52 4.4.4 利用不同停止電壓掃描流程 54 4.5 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)/TiN元件電流傳輸機制 56 4.5.1 Low voltage RRAM之電流傳輸機制 Fitting 56 4.5.2 High voltage RRAM之電流傳輸機制 Fitting 60 4.6 Pt/Hf:SiOx/Hf:SiOx(摻雜N2與NH3)/TiN元件可靠度分析 67 4.6.1 DC Sweep cycle 67 4.6.2 常溫Retention 69 4.7 元件應用: 多重記憶單元 (multi-bit) 70 4.8 模型建立 71 4.8.1 Low voltage RRAM模型建立 71 4.8.2 Middle voltage RRAM模型建立 72 4.8.3 High voltage RRAM模型建立 75 第五章 定電壓下電阻式記憶體Reset過程機制研究 78 5.1 氧化鉿薄膜電阻式記憶體(HfO2 RRAM) Ti/HfO2/TiN 78 5.2 電化學反應級數量測 78 5.3 電化學反應活化能Ea萃取 84 5.3.1 DC模式下的Constant Voltage Sampling 84 5.3.2 Fast I-V系統做Constant Voltage Sampling 92 5.4 實驗結果機制探討 98 5.4.1 DC模式下定電壓sampling 98 5.4.2 用Fast I-V系統做定電壓Sampling 100 5.5 模型建立 100 第六章 結論 105 參考文獻 107 |
參考文獻 References |
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