在本篇論文中，我們將探討ARM7微處理器之衍生架構。ARM7TDMI是ARM Ltd. 所發展的32位元RISC微處理器。它使用在嵌入式的運用上，像是行動電話、呼叫器和個人數位助理(PDA)。然而，隨著可攜性產品的功能多樣化要求更強大運算來處理。在本篇論文中我們將焦點放在ARM7微處理器之衍生架構的實作上，詳細描述從我們的RTL設計到其架構的衍生以及考量高效能及低閘數的討論。

In this paper, we will explore architecture variations of ARM7 microprocessors. The ARM7TDMI is a 32-bit microprocessor developed by ARM Ltd. It used in embedded application such as mobile phones, pager and PDAs. However, as portable products grow in complexity more processing power is required. This paper focuses on the implementation of the architecture variations of ARM7 microprocessors. The evolutions from our RTL design to architecture variations are described and the trade offs between high performance and low gate count discussed.

1. 簡介 1
1.1 研究動機 1
1.2 研究方法 1
1.3 論文大綱 3
2. 相關研究 4
2.1 ARM7TDMI 4
2.2 ARM8 5
2.3 ARM9 5
2.4 ARM ARCHITECTURE VARIANTS 7
3. SYS32TM微架構設計 10
3.1 管線式(PIPELINE)架構 10
3.2 指令提取階段(FETCH STAGE) 10
3.3 指令解碼階段(DECODE STAGE) 11
3.3.1 控制路徑 11
3.3.2 資料路徑 13
3.4 指令執行階段(EXECUTE STAGE) 14
3.4.1 資料路徑 14
3.4.2 條件式執行(Conditional Execution) 15
3.4.3 中斷控制 16
3.5 管線(PIPELINE)的控制 20
3.6 重要之延遲路徑(CRITICAL PATH) 22
3.6.1 改善Decode Stage之重要之延遲路徑 23
4. SYS32TME微架構設計 25
4.1 利用增加管線來提昇ARM7微處理器效能 25
4.1.1 設計動機(Motivation) 25
4.1.2 管線結構(Pipeline structure) 26
4.1.3 重新定義暫存器檔案(Regisger File) 28
4.2 5階管線式(5-STAGE PIPELINE)架構 31
4.2.1 管線化資料路徑 31
4.2.2 管線化控制 32
4.2.3 中斷(Interrupts)控制 37
4.3 解決管線危障(HAZARD)問題 39
4.3.1 資料危障(Data Hazard) 39
4.3.2 控制危障(Control Hazard) 42
4.3.3 暫存器寫回順序 43
4.4 驗證(VERIFICATION) 44
4.4.1 Verification strategy 44
4.4.2 自動化驗證環境 45
4.4.3 Systematic functional verification 49
4.4.4 Code Coverage 51
4.5 實作結果 52
4.5.1 Instruction cycle times 52
4.5.2 合成結果 53
4.5.3 效能及成本之比較 53
4.5.4 FPGA之實作 54
5. ARCHITECTURAL ALTERNATIVES 57
5.1 CRITICAL PATH REDUCTION 57
5.1.1 Critical Path 57
5.1.2 Forwarding Path Optimization 60
5.1.3 32-bit ARM instruction only 62
5.1.4 Writeback path optimization 63
5.1.5 Single execution mode 64
5.2 MMX INSTRUCTION SET SUPPORT 67
5.2.1 動機 67
5.2.2 架構描述及可行性分析 68
5.2.3 Software and Hardware Impact 71
5.3 16-BIT MICROPROCESSOR 73
5.3.1 動機 73
5.3.2 架構描述 74
5.3.3 評估效能及成本 75
6. 結論 76
7. 未來展望 78
8. 參考資料 79

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