以濺鍍方式鍍製CdTe薄膜，並且進行CdCl2熱處理。利用SEM觀察表面形貌，發現CdTe薄膜在熱處理前後，其晶粒大小由50~100 nm成長到1~3 μm，有再結晶(recrystallization)的現象。
新的元件結構設計如SLG/AZO/ZnO/CdS/CdTe/CI(G)S/Mo與典型的CdTe元件結構如SLG/FTO/CdS/CdTe/Cu/Au相比較，具有下列優點：(1) AZO/ZnO比FTO具備較佳的光穿透率和電性，(2) CdTe能隙值(Eg)為1.45 eV，加入Eg為1.04 eV的CuInSe2(簡稱CIS)可額外吸收1.04~1.45 eV之間的光，(3) CdTe具高能量障礙使其金屬背電極難以長久且穩定的使用，透過與CIS/Mo結合可形成良好的歐姆接觸(ohmic contact)，(4) Ga加入形成CI(G)S可調變薄膜能隙值梯度使光更有效被吸收，並由AMPS-1D之模擬得知此元件設計具有更高的轉換效率。
以基板在上(superstrate)疊層之元件結構製作太陽電池發現導通現象，嘗試以典型的CdTe元件結構製作太陽電池驗證CIS鍍膜過程對元件造成之破壞，而得CdTe元件之Voc為0.57 V，FF.為33.6%，轉換效率大約1.84%；並藉由理論計算得知Cu在CdTe薄膜層中具有快速的擴散能力進而解釋元件導通的原因。
　　另嘗試以SLG/Mo/CIS/CdTe/CdS/ZnO/AZO/Al之方式製作元件結構，發現有二極體效應但仍無轉換效率，減少CdTe薄膜厚度後，發現產生光電效應，其Voc為0.36 V，FF.為25.3%，轉換效率大約0.472%。判斷為CIS與CdTe之間晶格不符合(lattice mismatch)造成界面間形成過多的複合中心(recombination center)，使照光產生之載子被消滅。進一步透過退火處理使界面間互相擴散(interdiffusion)來減緩晶格不匹配狀況以消除複合中心，但另發現須解決殘餘應力(residual stress)在膜層間造成的剝離現象。

CdTe films were deposited by sputtering technique and were then carried out by CdCl2 treatment. The SEM micrographs show that the grain sizes of the as-deposited CdTe film were normally ranged from 50 nm to 100 nm, and they were recrystallized after CdCl2 treatment to obtain the grain sizes in the range of 1~3 μm.
A new device structure for CdTe thin-film solar cells has been proposed to exceed the cell efficiency of current record. The superstrate structure with the layer sequence of Glass/AZO/ZnO/CdS/CdTe/CI(G)S/Mo compared with the conventional device structure of Glass/FTO/CdS/CdTe/metal contact would have the following advantages:(1) a highly conductive AZO layer combined with a thin undoped ZnO layer will have higher optical transmission than that of FTO; (2) the use of p-type CIS under the CdTe layer with the same conductivity type can extend the light absorption to longer wavelength range (the band gaps of CdTe and CIS are 1.45eV and 1.04eV, respectively); (3) the proper addition of Ga to CIS may form CIGS quaternary compounds with a bandgap gradient which produce an electric field in the neutral region of a p-n junction to reduce the carrier recombination; (4) the use of Mo contact to CI(G)S is quite stable as compared with the metal contact normally used for p-CdTe. AMPS-1D simulation had been applied to evaluate the newly designed device structure and the results indicated a great improvement in device performance, i.e. the cell efficiency could exceed 20%.
The I-V curve of a CdTe solar cell using the new device structure showed a nearly linear characteristic indicating the failure to form a p-n junction. We speculated that Cu might diffuse through the CdTe layer to the depletion region of the p-n junction formed at the CdS/CdTe interface. This would cause the junction failure. Based on the calculation on the Cu diffusion during the deposition of CIS layer at different temperatures even as low as 150˚C, it always had the chance to diffuse through the CdTe layer.
An alternate device fabrication process was the use of the substrate structure for preparing CdTe solar cells, i.e. Glass/Mo/CIS/CdTe/CdS/ZnO/AZO/Al. However, the desired diode behavior was not observed until the thickness of CdTe layer was cut down to 10 nm. The electrical properties of that particular solar cell is the following:Voc=0.36V, Isc=4.991mA/cm2, F.F.=25.3%, efficiency=0.472%. It is probably that the lattice mismatch between CIS and CdTe is large that may cause the formation of interfacial defects and the reduction of photo excited carriers through the recombination processes. The annealing processes had been conducted in order to promote the interdiffusion between CdTe and CIS and minimize the lattice mismatch. However, the films peered off after annealing. Further experiments should be done to solve this problem.

致謝 ii
摘要 iii
目錄 vi
表目錄 viii
圖目錄 ix
一　緒論 1
1.1 簡介 1
1.2 太陽能電池元件介紹 1
1.2.1 太陽能電池原理 1
1.2.2 薄膜太陽能電池 2
1.3 CIS之材料性質與元件結構 4
1.4 CdTe薄膜材料製程與元件結構 7
1.5 新型高效率CdTe元件設計與模擬 15
1.6 實驗動機與目的 19
二 實驗內容 20
2.1 實驗儀器 20
2.1.1 蒸鍍系統 20
2.1.2 磁控濺鍍系統 21
2.1.3 快速升溫爐 22
2.1.4 化學水浴恆溫槽 23
2.2 實驗方法與步驟 23
2.2.1 玻璃基板準備 23
2.2.2 Cu-rich CIS層 24
2.2.3 CdTe層 24
2.2.4 CdCl2 熱處理 25
2.2.5 CdS層 25
2.2.6 濺鍍其他膜層 27
2.2.7 元件製作及發電效率計算 28
2.3 量測儀器 30
2.3.1 四點探針 30
2.3.2 電壓電流特性量測 30
2.3.3 穿透光譜 31
2.3.4 掃描式電子顯微鏡 31
2.3.5 X-ray繞射儀 31
三　研究結果與討論 33
3.1 CdTe薄膜濺鍍條件 33
3.1.1 基板溫度的影響 33
3.1.2 CdCl2熱處理 35
3.1.3 濺鍍與近距蒸鍍方法之結晶狀況比較 39
3.2 以基板在上之疊層方式製作元件 41
3.2.1 SLG/FTO/ZnO/CdS/CdTe/CIS/Mo元件結構之製作 41
3.2.2 調整CIS製程條件 43
3.2.3 SLG/FTO/CdS/CdTe/Sb/Mo元件結構之製作 45
3.2.4 銅元素擴散之理論計算 48
3.3 以基板在下之疊層方式製作元件 52
3.3.1 SLG/Mo/CIS/CdTe/CdS/ZnO/AZO/Al元件結構之製作 52
3.3.2 CdTe厚度調整 53
3.3.3 以GIXRD觀察CdTe/CIS界面互相擴散現象 55
3.3.4 熱處理的問題 58
四　結論 62
五　參考文獻 64

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