根據相關的研究數據，目前多數的IC設計個案中，RTL階段的驗證工作佔了整個設計流程約60%~80%左右的時間。當我們想要針對微處理器產生測試樣本進行功能性驗證 (Functional verification) 的時候，從”指令集架構”出發應該是一個合理且可行的方法。在本篇論文中所提出的指令測試樣本(instruction test pattern)產生器，即是根據使用者描述的指令集架構幫助使用者產生微處理器的功能驗證時所需要的測試樣本。
本報告中的產生器包括三個基本的流程：各別指令、指令對、和手寫產生指令。它們的用處在於不同目的的驗證，各別指令可以將指令集架構中定義的指令產生出來，可以用來驗證每一個各別指令的動作是否正確﹔指令對則是驗證在一個管線化的微處理器架構下指令之間的相互作用關係﹔手寫產生的指令則是為了驗證一些特殊的狀況(corner cases)。
關於本論文中如何評估產生器所產生的測試樣本的品質(quality)，我們實際產生32位元的指令集(ARM指令集、SPARC指令集)並對其中一個可合成的RTL核心進行驗證，搭配少部分(34.7%)手寫的測試樣本即可將程式涵蓋率(HDL code coverage)達到100%，這個結果可以用來當作評估測試樣本的品質的參考依據。
因為本報告中的產生器是根據指令的欄位產生測試樣本，所以針對不同的指令集架構皆可以在不更動程式的情況下重複使用(即所謂retargetable)，除了精簡指令集的指令集架構之外，甚至複雜指令集的測試樣本亦可產生。

When we survey hardware design groups, we can find that it is now dedicated to verification between 60 to 80 percent. According to the instruction set architecture information should be a feasible and reasonable way for generating the test pattern to verify the function of a microprocessor. In this these, we’ll present an instruction test pattern (for microprocessors) generation method based on the instruction set architecture. It can help the users to generate the instruction test pattern efficiently.
The generation flow in this thesis contains three major flows: individual instruction, instruction pair, and manual generation. They are used for different verification cases. The “individual instruction” could be used for verifying the functions of each implemented instructions. The “instruction pair” could be used for verifying the interaction of instruction execution in a pipeline for a HDL implementation of a microprocessor. The “manual generation” could be used to verify some corner cases (behaviors) of the microprocessor.
As the quality of our test pattern, we generate some patterns for 32-bits instruction (ARM instruction sets and SPARC instruction sets) and use them to verify a synthesizable RTL core. With some handwriting test pattern (34.7%), our automatic generation method can approach 100% HDL code coverage of the microprocessor design. We use the HDL code coverage as the reference of test pattern quality.
Because our generation method is based on the instruction field, we can describe most instruction set for the generator. Hence, our generation method can retarget to most instruction set architecture without modifying the generator. Besides the RISC instructions, even the CISC instructions could be generated.

Contents
1、 Introduction 3
1.1 Motivation 3
1.2 Research Scope 3
1.3 Scheme of This Thesis 4
2、 Related Work 5
2.1 Fault Coverage and ATPG Tools 5
2.2 Test Pattern Generation and Simulation-Based Verification 5
2.3 Instruction Set Architecture and Functional Verification 6
2.4 Code Coverage 6
2.5 A Published Test Pattern Generator 7
3、 Instruction Set Architecture 13
3.1 Instruction format 13
3.2 Instruction Set Operation 16
3.3 Operand Semantics 17
3.4 Pre/Post Instructions 20
4、 Generation Method Implementation 24
4.1 Specification for Instruction Description 24
4.2 Generation Flow 34
4.3 Timing/Space Complexity 36
4.5 Program Structure 37
4.6 How To Use This Tool 39
5、 HDL Code Coverage 43
5.1 The Related Research 43
5.2 Coverage Definition 43
6、 Case Study: ARM Instruction Set 47
6.1 ARM instruction format 47
6.2 The Sequential Instructions 54
6.3 The Branch (include the PC related) Instructions 56
6.4 Other Instructions 58
6.5 Experiment Result 59
7、 Case Study: SPARC Instruction Set 65
7.1 SPARC Instruction Format 65
7.2 Automatically Generated Instructions 70
7.3 Manually Generated Instructions 71
7.4 Experiment Result 74
8、 Discussion 75
8.1 What the Code Coverage Means? 75
8.2 Implementation Language 75
8.3 Automation Performance 76
8.4 Reducing the Pattern Size 78
8.5 Limitation of Instruction Test-Pattern 78
8.6 HDL Code Variations 79
9、 Conclusion 82
10、 Reference 83
11、 Appendix 85
11.1 The test-bench 85
11.2 The verification plan 85
11.3 User’s Manual 86

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