此篇重點著重於部分空乏-矽覆絕緣電晶體(Partially Depleted Silicon on Insulator，PD-SOI)之浮體效應(Floating Body Effect)上，由於傳統的部分空乏-矽覆絕緣單電晶體隨機存取記憶體單元(PD-SOI 1T-DRAM Cell)無法有效地把部分空乏-矽覆絕緣電晶體因碰撞游離而產生的電洞保留住，因此傳統部分空乏-矽覆絕緣電晶體無法提供記憶體有效地資料鑑別率。因此在這篇論文中，我們提出一個新元件結構，除了在元件本體(Body)的兩側中增加了阻擋氧化層(Block Oxide)，以加強其屈膝效應(Kink Effect)外，還在元件U型槽下方的基底(Substrate)部分增加負偏壓，使其屈膝效應的操控更加容易，更加強元件保留其電洞的能力，改善傳統部分空乏-矽覆絕緣單電晶體隨機存取記憶體單元的性能。

此一新矽覆絕緣元件的結構具有下列四項特點：
1. 利用傳統矽晶片即可製作。不需用到昂貴的矽覆絕緣晶片。
2. 提高單電晶體隨機存取記憶體單元規劃視窗(Programming Window)。
3. 避免源極和汲極空乏區夾止(Pinch off)。
4. 減少源極-本體和汲極-本體的接面電容。
我們使用模擬工具ISE TCAD 10.0模擬出新元件的結構，再對模擬出來的元件結構做I-V曲線的電性分析。在製程上，我們運用國家奈米實驗室（NDL）的機台設備來實際製作這項元件。

This article focuses on “Floating Body Effect” of PD-SOI (partial depletion silicon-on-insulator), because the conventional PD-SOI 1T DRAM (one transistor of dynamic random access memory) cell can’t be held impact ionization produced carriers efficiently, so it is unable to provide reliable programming window. In this article, we propose a new device with its special structure, besides adding “Block Oxide” to the two sides of device body to strengthen “kink effect”, we also add a negative bias to the beneath electrode which is located in the bottom of U-cave of this device, this design can manipulate “kink effect” more feasibly, and guarantee the hole-held ability. Those points can improve performance of PD-SOI 1T DRAM cell greatly.

The new SOI device contains four advantages in the below:

1. Exploiting conventional bulk Si-wafer for manufacture, no expensive SOI wafer needs.
2. Increasing programming window of 1T DRAM cell greatly.
3. Preventing “Pinch off” occurs in source and drain depletion region.
4. Reducing the junction capacitor of Source-Body and Drain-Body.

We use simulation tool, ISE TCAD 10.0 to simulate structure of this new device, and do I-V characteristic electric analyze to this device. In the manufacture, thanks for the equipment and facility of NDL (National Device Laboratory); we apply to this resource to realize our devices.

英文摘要 II
中文摘要 III
致謝 IV
目錄 V
圖目錄 VII

第一章 緒論 1
1-1 動態隨機存取記憶體(DRAM)歷史發展1
1-2 單電晶體動態隨機存取記憶體之簡介5
1-3 單電晶體動態隨機存取記憶體之操作原理6

第二章 各種無電容動態隨機存取記憶體元件的簡介10
2-1 A Capacitorless DRAM Cell on SOI Substrate10
2-1-1 無電容動態隨機存取記憶體(CDRAM)之簡介10
2-1-2無電容動態隨機存取記憶體之操作原理11
2-2 FBC(Floating Body Cell) for Embedded DRAM on SOI12
2-2-1 浮體單元製程之簡介12
2-2-2 浮體單元之操作原理12
2-3 A Capacitorless Double Gate DRAM Technology for Sub-100- nm Embedded and Stand-Alone Memory Applications13
2-3-1 雙閘極動態隨機存取記憶體製程之簡介13
2-3-2 雙閘極動態隨機存取記憶體之操作原理14
2-4 A Capacitor-less DRAM Cell on 75nm Gate Length, 16nm thin Fully Depleted SOI Device for High Density Embedded Memories15
2-4-1 全空乏動態隨機存取記憶體製程之簡介15
2-4-2 全空乏動態隨機存取記憶體之原理操作16
2-5 Fully-Depleted FBC (Floating Body Cell) with Enlarged Signal Window and Excellent Logic Process Compatibility17
2-5-1 全空乏浮體動態隨機存取記憶體單元之製程簡介17
2-5-2 全空乏浮體動態隨機存取記憶體單元之操作原理19
2-6 A New 1T DRAM Cell With Enhanced Floating Body Effect 19
2-6-1具阻擋氧化層的部分隔離電晶體(bMPI)之製程步驟19
2-6-2具阻擋氧化層的部分隔離電晶體之操作原理20

第三章 新元件結構的模擬22
3-1 三種元件(U井電晶體、阻擋氧化層的部分隔離電晶體、部分空乏矽覆絕緣電晶體)結構說明22
3-2三種元件(U井電晶體、阻擋氧化層的部分隔離電晶體、部分空乏矽覆絕緣電晶體)電性模擬25
3-2-1 屈膝效應之討論25
3-2-2 規劃視窗之討論27
3-3 新元件架構的探討分析28

第四章 U井電晶體結構的設計與製作32
4-1 U井電晶體結構設計流程32
4-2 實作製程下的光罩與場發射掃描式電子顯微鏡(SEM)圖36
4-2-1 定義U井區36
4-2-2 定義主動區和閘極37
4-2-3 定義接觸洞區域和金屬區域38

第五章 實驗結果41

第六章 結論 43

參考文獻44

附錄A46

[1]M. Elahy, H. Shichijo, P. K. Chatterjee, A. H. Shah, S. K. Banerjee, and R. H. Womack, “Trench Capacitor Leakage in High-Density DRAM's,” IEEE Electron Device Lett., vol. 5, no. 12, pp.527-530, Sept. 2000.
[2]K. Kim and M. Y. Jeong, “The COB Stack DRAM Cell at Technology Node below 100 nm-Scaling Issues and Directions,” IEEE Trans. Semiconductor Manufacturing, vol. 15, no. 2, pp. 137-143, May 2002.
[3]N. Sakimura, T. Sugibayashi, T. Honda, H. Honjo, S. Saito, T. Suzuki, N. Ishiwata, and S. Tahara, “MRAM Cell Technology for Over 500-MHz SoC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 830-838, April. 2007.
[4]P. Fantini, A. Benvenuti, A. Pirovano, F. Pellizzer, D. Ventrice, and G. Ferrari, “A Compact Model for Phase Change Memories,” SISPAD Int. Conf., pp. 162-165, Sept. 2006.
[5]H. J. Wann and C. Hu, “A Capacitorless DRAM Cell on SOI Substrate,” in IEDM Tech. Dig., pp. 635-638, Dec. 1993.
[6]S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI Capacitor-less 1T-DRAM Concept,” IEEE Int. SOI Conf., pp.153–154, Oct. 2001.
[7]S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, ” A Capacitor-Less 1T-DRAM Cell,” IEEE Electron Device Lett., vol. 23, no. 2, pp. 85-87, Feb. 2002.
[8]P. C. Fazan, S. Okhonin, M. Nagoga, and J. M. Sallese, “A Simple 1-transistor Capacitor-less Memory Cell for High Performance Embedded DRAMs,” in Proc. IEEE Custom Integrated Circuits Conf., pp. 99-102, May 2002.
[9]P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, and M. Declercq, “Capacitor-less 1-transistor DRAM,” in Proc. Int. SOI Conf., pp. 10-13, Oct. 2002.
[10]T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, and K. Sunouchi, “Memory Design Using a One-transistor Gain Cell on SOI,” IEEE J. Solid-State Circuits, vol. 37, no. 11, pp. 1510-1522, Nov. 2002.
[11]C. Kuo, T. J. King, and C. Hu, “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications,” in IEDM Tech. Dig., pp. 843-846, Dec. 2002.
[12]K. Inoh, T. Shino, H. Yamada, H. Nakajima, Y. Minami, T. Yamada, T. Ohsawa, T. Higashi, K. Fujita, T. Ikehashi, T. Kajiyama, Y. Fukuzumi, T. Hamamoto, and H. Ishiuchi, ” FBC (Floating Body Cell) for Embedded DRAM on SOI,” in Symp. VLSI Tech. Dig., pp. 63-64, June 2003.
[13]C. Kuo, T. J. King, C. Hu, “A Capacitorless Double Gate DRAM Technology for Sub-100-nm Embedded and Stand-alone Memory Applications,” IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2408-2416, Dec. 2003.
[14]E. Yoshida, and T. Tanaka, “A Design of a Capacitorless 1T-DRAM Cell Using Gate-Induced Drain Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” in IEDM Tech. Dig., pp. 37.6.1-37.6.4, Dec. 2003.
[15]T. Shino, I. Higashi, K. Fujita, T. Ohsawa, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, “Highly Scalable FBC (Floating Body Cell) with 25nm BOX Structure for Embedded DRAM Applications,” in Symp. VLSI Tech. Dig., pp. 132-133, June 2004.
[16]T. Tanaka, E. Yoshida, and T. Miyashita, “Scalability Study on a Capacitorless 1T-DRAM: From Single-Gate PD-SOI to Double-Gate FinDRAM,” in IEDM Tech. Dig. pp. 919-922, Dec. 2004.
[17]R. Ranica, A. Villaret, C. Fenouillet-Beranger, P. Malinge, P. Mazoyer, P. Masson, D. Delille, C. Charbuillet, P. Candelier, and T. Skotnicki, “A Capacitor-less DRAM Cell on 75nm Gate Length, 16nm Thin Fully Depleted SOI Device for High Density Embedded Memories,” in IEDM Tech. Dig., pp. 277-280, Dec. 2004.
[18]T. Shino, T. Higashi, N. Kusunoki, K. Fujita, T. Ohsawa, N. Aoki, H. Tanimoto, Y. Minami, T. Yamada, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, “Fully-depleted FBC (floating body cell) with Enlarged Signal Window and Excellent Logic Process Compatibility,” in IEDM Tech. Dig. pp. 281-284, Dec. 2004.
[19]T. Shino, T. Ohsawa, T. Higashi, K. Fujita, N. Kusunoki, Y. Minami, M. Morikado, H. Nakajima, K. Inoh, T. Hamamoto, and A. Nitayama, “Operation Voltage Dependence of Memory Cell Characteristics in Fully Depleted Floating-Body Cell,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2220-2226, Oct. 2005.
[20]E. Yoshida, and T. Tanaka, “A Capacitorless 1T-DRAM Technology Using Gate-Induced Drain-Leakage (GIDL) Current for Low-Power and High-Speed Embedded Memory,” IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 692-697, April 2006.
[21] J. T. Lin and M. Chang, “A New 1T DRAM Cell with Enhanced Floating Body Effect,” in Proc. IEEE Int. MTDT, 5 pp. Aug. 2006.