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博碩士論文 etd-0830107-153451 詳細資訊
Title page for etd-0830107-153451
論文名稱
Title
結合共振帶間穿隧二極體(RITD)和互補金屬氧化半導體技術之新SRAM元件製作
A New SRAM Device Based on RITD (Resonant Interband Tunneling Diode) and CMOS Technology
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
58
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-16
繳交日期
Date of Submission
2007-08-30
關鍵字
Keywords
互補金屬氧化半導體、共振帶間穿隧二極體
SRAM, RITD
統計
Statistics
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中文摘要
本論文利用在傳統金屬氧化物半導體(MOS)的源極和汲極上方和下方製造出一對共振帶間穿隧二極體RITD(Resonant Interband Tunnel Devices)元件,此結構在製作上是依沉積,蝕刻及側邊技術來完成,製程步驟雖因共振帶間穿隧二極體的製作而略顯繁複,但並不非常困難。此單一金屬氧化物半導體元件,在源極和汲極上方和下方製造出一對共振帶間穿隧二極體,其等效模型可視作一在傳統上需六個電晶體才能完成的靜態隨機存取記憶體(SRAM),因此無論在體積,成本的考量上都佔優勢,此外因共振帶間穿隧二極體具高速度及低功率,此元件亦能符合靜態隨機存取記憶體要求的特點,又因工作機制的不同,此元件比較傳統靜態隨機存取記憶體,在接線和操作上都較為簡易,亦為其另一優點。
  本論文將揭示此一元件的製作過程,及解釋其等效電路和工作原理。
Abstract
This thesis proposes a new architecture, fabricating a pair of RITD (Resonant Interband Tunnel Diode) in the upper and lower position of drain and source terminals of a conventional MOS (Metal oxide Semiconductor), this design is completed by deposition, etching and spacer sequentially, manufacture process is a little complicate due to RITD implementation, but not difficult. This MOS based device, given to a pair of RITD in the upper and lower position of drain and source terminals, its equal model is like a conventional SRAM (Static Random Access Memory) which is completed by six MOS components at least, thus given advantages, like space occupation, cost consideration, still, due to high speed switch and low power consumption of RITD, this device also meet requirement of SRAM, because of different working mechanism, this device is more simple in interconnection and operation than that of a conventional SRAM, it is another improvement.
This thesis will exhibit the manufacture process of this device and its equal circuit mode and working explanation.
目次 Table of Contents
英文摘要 ……………………………………………………………………… I
中文摘要 ……………………………………………………………………… II
致謝 ………………………………………………………………………… III
目錄 ………………………………………………………………………… IV
第一章 導論 ……………………………………………………………………… 1
1-1 前言 ………………………………………………………………… 1
1-2 靜態隨機存取記憶體簡介 ……………………………………… 2
1-3 共振帶間穿遂二極體介紹 ………………………………………… 3
1-4 文獻探討 …………………………………………………………… 5
1-5 研究動機 …………………………………………………………… 16
第二章 元件設計與實際製程 …………………………………………………… 18
2-1元件設計與說明……………………………………………………… 18
2-2 元件結構製程 ……………………………………………………… 24
2-3 元件架構特性 ……………………………………………………… 28
第三章 元件模擬比較 …………………………………………………………… 31
3-1防護電壓比較 ……………………………………………………… 31
3-2 消耗功率比較 ……………………………………………………… 33
3-3 製程上的比較 ……………………………………………………… 35
第四章 結論與未來發展 ………………………………………………………… 36
4-1 結論 ………………………………………………………………… 36
4-2 未來發展 …………………………………………………………… 37
參考文獻 …………………………………………………………………………… 38
附件A HSPICE模擬 …………………………………………………………… 40
附件B 完整製程 ………………………………………………………………… 42
參考文獻 References
[1] S. Sudirgo, B. Curanovic, S. L. Rommel, K. D. Hirschman, S. K. Kurinec, N. Jin, A. T. Rice, P. R. Berger, P. E. Thompson, “Challenges in Integration of Resonant Interband Tunnel Devices with CMOS ,” Symp. IEEE 15th Biennial , pp. 275-278, July 2003.
[2] N. Jin, S. Y. Chung, A. T. Rice, and P. R. Berger, R. Yu, P. E. Thompson, R. Lake, “151 kA/cm2 peak current densities in Si/SiGe resonant interband tunneling diodes for high-power mixed-signal applications,” Appl. Phys. Lett., vol. 83, no. 16, pp. 3308-3310, Oct. 2003.
[3] S. Y. Chung, N. Jin, P. R. Berger, R. Yu, P. E. Thompson, R. Lake, S. L. Rommel, S. K. Kurinec, “Three-terminal Si-based negative differential resistance circuit element with adjustable peak-to-valley current ratios using a monolithicvertical integration,” Appl. Phys. Lett., vol. 84, no. 14, pp. 2688-2690, April 2004.
[4] K. Morimoto, H. Sorada, K. Morita, “Monolithic integration of Si-interband tunneling diodes with a MOSFET for ultralow voltage operation static random access memory,” FED Journal, 2000.
[5] R. Duschl, O. G. Schmidt, C. Reitemann, E. Kasper, K. Eberl, “High Room Temperature Peak-to-Valley Current Ratio in Si Based Esaki Diodes,” IEEE Electronics Lett., vol. 35, no. 13, pp. 2688-2690, June 1999.
[6] R. Duschl, O. G. Schmidt, K. Eberl, “Epitaxially Grown Si/SiGe Interband Tunneling Diodes with High Room-Temperature Peak-to- Valley Ratio,“ Appl. Phys. Lett., vol. 76, no. 7, pp. 879-881, Feb. 2000.
[7] U. Auer, W. Prost, M. Agethen, F. J. Tegude, R. Duschl, K. Eber, “Low-Voltage MOBILE Logic Module Based on Si/SiGe Interband Tunnelling Diodes,” IEEE Electron Device Lett., vol. 22, no. 5, pp. 215-217, May 2001.
[8] S. Sudirgo, R. Vega, R. P. Nandgaonkar, K. D. Hirschman, S. L. Rommel, S. K. Kurineca, P. E. Thompsonb, N. Jin , and P. R. Bergerc, “Overgrown Si/SiGe Resonant Interband Tunnel Diodes for Integration with CMOS,” IEEE Electron Device Lett., vol. 1, pp. 109-110, June 2004.
[9] N. Jin, S. Y. Chung, A. T. Rice, P. R. Berger, P. E. Thompson, S. C. Rivas, R. Lake, S. Sudirgo, J. J. Kempisty, B. Curanovic, S. L. Rommel,, K. D. Hirschman , S. K. Kurinec, P. H. Chi, D. S. Simons, “Diffusion Barrier Cladding in Si/SiGe Resonant Interband Tunneling Diodes and Their Patterned Growth on PMOS Source/Drain Regions,” IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1876-1884, Sept. 2003.
[10] S. Sudirgo, R. P. Nandgaonkar, B. Curanovic, J. L. Hebding, R. L. Saxer, S. S. Islam, K. D. Hirschman, S. L. Rommel, S. K. Kurinec, P. E. Thompson, N. Jin, P. R. Berger, “Monolithically integrated Si/SiGe resonant interband tunnel diode/CMOS demonstrating low voltage MOBILE operation,” Solid-State Electronics, pp. 1907-1910, March 2004.
[11] N. Jin, S. Y. Chung, R. M. Heyns, P. R. Berger, R. Yu, P. E. Thompson, S. L. Rommel, “Phosphorus diffusion in Si-based resonant interband tunneling diodes and tri-state logic using vertically stacked diodes,” Materials Science in Semiconductor Processing, pp. 411-416, Oct. 2005 .
[12] N. Jin, Anthony T. Rice, P. R. Berger, P. E. Thompson, P. H. Chi, D. S. Simons, “SiGe Diffusion Barriers for P-doped Si/SiGe Resonant Interband Tunnel Diodes,” Proc. IEEE Lester Eastman Conf., pp. 411-416, Aug. 2002.
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